mirror of
https://github.com/brain-hackers/u-boot-brain
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![andrey.konovalov@linaro.org](/assets/img/avatar_default.png)
Commit 4a271cb1b4
doesn't take into account that fdtdec_setup_gpio()
returns success when the gpio passed to it is FDT_GPIO_NONE (no
gpio node found in the fdtdec_decode_gpio() call). This results in
calling gpio_direction_output() on invalid gpio. For this reason
executing "usb start" command on Arndale causes data abort in the
ehci-exynos driver.
Add the fdt_gpio_isvalid() check to fix that problem.
Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
329 lines
7.8 KiB
C
329 lines
7.8 KiB
C
/*
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* SAMSUNG EXYNOS5 USB HOST XHCI Controller
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Vivek Gautam <gautam.vivek@samsung.com>
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* Vikas Sajjan <vikas.sajjan@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This file is a conglomeration for DWC3-init sequence and further
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* exynos5 specific PHY-init sequence.
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <malloc.h>
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#include <usb.h>
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#include <watchdog.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/power.h>
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#include <asm/arch/xhci-exynos.h>
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#include <asm/gpio.h>
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#include <asm-generic/errno.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* Contains pointers to register base addresses
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* for the usb controller.
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*/
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struct exynos_xhci {
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struct exynos_usb3_phy *usb3_phy;
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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struct fdt_gpio_state vbus_gpio;
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};
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static struct exynos_xhci exynos;
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#ifdef CONFIG_OF_CONTROL
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static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos)
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{
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fdt_addr_t addr;
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unsigned int node;
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int depth;
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node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI);
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if (node <= 0) {
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debug("XHCI: Can't get device node for xhci\n");
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return -ENODEV;
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}
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/*
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* Get the base address for XHCI controller from the device node
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*/
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addr = fdtdec_get_addr(blob, node, "reg");
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if (addr == FDT_ADDR_T_NONE) {
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debug("Can't get the XHCI register base address\n");
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return -ENXIO;
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}
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exynos->hcd = (struct xhci_hccr *)addr;
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/* Vbus gpio */
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fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
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depth = 0;
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node = fdtdec_next_compatible_subnode(blob, node,
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COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
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if (node <= 0) {
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debug("XHCI: Can't get device node for usb3-phy controller\n");
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return -ENODEV;
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}
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/*
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* Get the base address for usbphy from the device node
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*/
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exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node,
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"reg");
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if (exynos->usb3_phy == NULL) {
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debug("Can't get the usbphy register address\n");
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return -ENXIO;
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}
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return 0;
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}
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#endif
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static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
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{
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u32 reg;
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/* enabling usb_drd phy */
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
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/* Reset USB 3.0 PHY */
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writel(0x0, &phy->phy_reg0);
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clrbits_le32(&phy->phy_param0,
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/* Select PHY CLK source */
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PHYPARAM0_REF_USE_PAD |
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/* Set Loss-of-Signal Detector sensitivity */
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PHYPARAM0_REF_LOSLEVEL_MASK);
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setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
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writel(0x0, &phy->phy_resume);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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setbits_le32(&phy->link_system,
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LINKSYSTEM_XHCI_VERSION_CONTROL |
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LINKSYSTEM_FLADJ(0x20));
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/* Set Tx De-Emphasis level */
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clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
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setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
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setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
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/* PHYTEST POWERDOWN Control */
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clrbits_le32(&phy->phy_test,
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PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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/* UTMI Power Control */
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writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
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/* Use core clock from main PLL */
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reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
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/* Default 24Mhz crystal clock */
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PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
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PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88) |
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/* Force PortReset of PHY */
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PHYCLKRST_PORTRESET |
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/* Digital power supply in normal operating mode */
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PHYCLKRST_RETENABLEN |
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/* Enable ref clock for SS function */
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PHYCLKRST_REF_SSP_EN |
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/* Enable spread spectrum */
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PHYCLKRST_SSC_EN |
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/* Power down HS Bias and PLL blocks in suspend mode */
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PHYCLKRST_COMMONONN;
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writel(reg, &phy->phy_clk_rst);
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/* giving time to Phy clock to settle before resetting */
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udelay(10);
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, &phy->phy_clk_rst);
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}
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static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
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{
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setbits_le32(&phy->phy_utmi,
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PHYUTMI_OTGDISABLE |
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PHYUTMI_FORCESUSPEND |
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PHYUTMI_FORCESLEEP);
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clrbits_le32(&phy->phy_clk_rst,
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PHYCLKRST_REF_SSP_EN |
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PHYCLKRST_SSC_EN |
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PHYCLKRST_COMMONONN);
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/* PHYTEST POWERDOWN Control to remove leakage current */
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setbits_le32(&phy->phy_test,
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PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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/* disabling usb_drd phy */
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
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}
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void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
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{
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clrsetbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(mode));
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}
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static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_CORESOFTRESET);
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->g_usb3pipectl[0],
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DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->g_usb2phycfg,
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DWC3_GUSB2PHYCFG_PHYSOFTRST);
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mdelay(100);
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
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DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb2phycfg,
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DWC3_GUSB2PHYCFG_PHYSOFTRST);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_CORESOFTRESET);
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}
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static int dwc3_core_init(struct dwc3 *dwc3_reg)
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{
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u32 reg;
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u32 revision;
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unsigned int dwc3_hwparams1;
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revision = readl(&dwc3_reg->g_snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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puts("this is not a DesignWare USB3 DRD Core\n");
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return -EINVAL;
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}
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dwc3_core_soft_reset(dwc3_reg);
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
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reg = readl(&dwc3_reg->g_ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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debug("No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if ((revision & DWC3_REVISION_MASK) < 0x190a)
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reg |= DWC3_GCTL_U2RSTECN;
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writel(reg, &dwc3_reg->g_ctl);
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return 0;
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}
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static int exynos_xhci_core_init(struct exynos_xhci *exynos)
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{
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int ret;
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exynos5_usb3_phy_init(exynos->usb3_phy);
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ret = dwc3_core_init(exynos->dwc3_reg);
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if (ret) {
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debug("failed to initialize core\n");
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return -EINVAL;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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return 0;
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}
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static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
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{
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exynos5_usb3_phy_exit(exynos->usb3_phy);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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struct exynos_xhci *ctx = &exynos;
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int ret;
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#ifdef CONFIG_OF_CONTROL
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exynos_usb3_parse_dt(gd->fdt_blob, ctx);
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#else
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ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();
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ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();
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#endif
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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#ifdef CONFIG_OF_CONTROL
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/* setup the Vbus gpio here */
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if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
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!fdtdec_setup_gpio(&ctx->vbus_gpio))
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gpio_direction_output(ctx->vbus_gpio.gpio, 1);
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#endif
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ret = exynos_xhci_core_init(ctx);
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if (ret) {
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puts("XHCI: failed to initialize controller\n");
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return -EINVAL;
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}
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*hccr = (ctx->hcd);
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*hcor = (struct xhci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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void xhci_hcd_stop(int index)
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{
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struct exynos_xhci *ctx = &exynos;
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exynos_xhci_core_exit(ctx);
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}
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