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https://github.com/brain-hackers/u-boot-brain
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940185910f
Assembler is not happy:
arch/x86/cpu/call32.S: Assembler messages:
arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 6f92ed8f1a ("x86: Add a way to call 32-bit code from 64-bit mode")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
63 lines
1.2 KiB
ArmAsm
63 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <asm/global_data.h>
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#include <asm/msr-index.h>
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#include <asm/processor-flags.h>
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/*
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* rdi - 32-bit code segment selector
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* rsi - target address
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* rdx - table address (0 if none)
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*/
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.code64
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.globl cpu_call32
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cpu_call32:
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cli
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/* Save table pointer */
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mov %edx, %ebx
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/*
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* Debugging option, this outputs characters to the console UART
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* mov $0x3f8,%edx
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* mov $'a',%al
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* out %al,(%dx)
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*/
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pushf
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push %rdi /* 32-bit code segment */
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lea compat(%rip), %rax
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push %rax
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retfq
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.code32
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compat:
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/*
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* We are now in compatibility mode with a default operand size of
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* 32 bits. First disable paging.
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*/
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movl %cr0, %eax
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andl $~X86_CR0_PG, %eax
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movl %eax, %cr0
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/* Invalidate TLB */
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xorl %eax, %eax
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movl %eax, %cr3
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/* Disable Long mode in EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btr $_EFER_LME, %eax
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wrmsr
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/* Set up table pointer for _x86boot_start */
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mov %ebx, %ecx
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/* Jump to the required target */
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pushl %edi /* 32-bit code segment */
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pushl %esi /* 32-bit target address */
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retfl
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