mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
81 lines
1.8 KiB
C
81 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
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*/
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#ifndef _SYSTEM_MANAGER_ARRIA10_H_
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#define _SYSTEM_MANAGER_ARRIA10_H_
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struct socfpga_system_manager {
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u32 siliconid1;
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u32 siliconid2;
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u32 wddbg;
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u32 bootinfo;
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u32 mpu_ctrl_l2_ecc;
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u32 _pad_0x14_0x1f[3];
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u32 dma;
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u32 dma_periph;
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u32 sdmmcgrp_ctrl;
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u32 sdmmc_l3master;
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u32 nand_bootstrap;
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u32 nand_l3master;
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u32 usb0_l3master;
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u32 usb1_l3master;
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u32 emac_global;
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u32 emac[3];
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u32 _pad_0x50_0x5f[4];
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u32 fpgaintf_en_global;
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u32 fpgaintf_en_0;
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u32 fpgaintf_en_1;
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u32 fpgaintf_en_2;
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u32 fpgaintf_en_3;
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u32 _pad_0x74_0x7f[3];
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u32 noc_addr_remap_value;
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u32 noc_addr_remap_set;
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u32 noc_addr_remap_clear;
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u32 _pad_0x8c_0x8f;
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u32 ecc_intmask_value;
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u32 ecc_intmask_set;
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u32 ecc_intmask_clr;
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u32 ecc_intstatus_serr;
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u32 ecc_intstatus_derr;
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u32 mpu_status_l2_ecc;
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u32 mpu_clear_l2_ecc;
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u32 mpu_status_l1_parity;
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u32 mpu_clear_l1_parity;
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u32 mpu_set_l1_parity;
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u32 _pad_0xb8_0xbf[2];
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u32 noc_timeout;
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u32 noc_idlereq_set;
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u32 noc_idlereq_clr;
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u32 noc_idlereq_value;
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u32 noc_idleack;
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u32 noc_idlestatus;
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u32 fpga2soc_ctrl;
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u32 _pad_0xdc_0xff[9];
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u32 tsmc_tsel_0;
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u32 tsmc_tsel_1;
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u32 tsmc_tsel_2;
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u32 tsmc_tsel_3;
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u32 _pad_0x110_0x200[60];
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u32 romhw_ctrl;
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u32 romcode_ctrl;
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u32 romcode_cpu1startaddr;
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u32 romcode_initswstate;
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u32 romcode_initswlastld;
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u32 _pad_0x214_0x217;
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u32 warmram_enable;
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u32 warmram_datastart;
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u32 warmram_length;
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u32 warmram_execution;
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u32 warmram_crc;
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u32 _pad_0x22c_0x22f;
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u32 isw_handoff[8];
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u32 romcode_bootromswstate[8];
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};
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
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#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
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