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https://github.com/brain-hackers/u-boot-brain
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4916388a39
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers Access Control register offset is 0x50. Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
23 lines
395 B
C
23 lines
395 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*/
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#ifndef __SOCFPGA_SCU_H__
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#define __SOCFPGA_SCU_H__
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struct scu_registers {
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u32 ctrl; /* 0x00 */
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u32 cfg;
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u32 cpsr;
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u32 iassr;
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u32 _pad_0x10_0x3c[12]; /* 0x10 */
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u32 fsar; /* 0x40 */
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u32 fear;
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u32 _pad_0x48_0x4c[2];
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u32 acr; /* 0x50 */
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u32 sacr;
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};
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#endif /* __SOCFPGA_SCU_H__ */
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