mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
0b8f6378cb
The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
36 lines
662 B
C
36 lines
662 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef _MISC_H_
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#define _MISC_H_
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void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
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struct bsel {
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const char *mode;
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const char *name;
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};
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extern struct bsel bsel_str[];
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#ifdef CONFIG_FPGA
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void socfpga_fpga_add(void);
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#else
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static inline void socfpga_fpga_add(void) {}
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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void socfpga_sdram_remap_zero(void);
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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void socfpga_init_security_policies(void);
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void socfpga_sdram_remap_zero(void);
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#endif
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void do_bridge_reset(int enable);
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#endif /* _MISC_H_ */
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