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https://github.com/brain-hackers/u-boot-brain
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b924d586d7
Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Tom Rini <trini@ti.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
84 lines
1.9 KiB
ArmAsm
84 lines
1.9 KiB
ArmAsm
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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ENTRY(armv8_switch_to_el2)
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switch_el x0, 1f, 0f, 0f
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0: ret
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1:
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mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
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msr scr_el3, x0
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msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
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/* Initialize SCTLR_EL2 */
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msr sctlr_el2, xzr
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/* Return to the EL2_SP2 mode from EL3 */
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mov x0, sp
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msr sp_el2, x0 /* Migrate SP */
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mrs x0, vbar_el3
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msr vbar_el2, x0 /* Migrate VBAR */
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mov x0, #0x3c9
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msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
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msr elr_el3, lr
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eret
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ENDPROC(armv8_switch_to_el2)
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ENTRY(armv8_switch_to_el1)
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switch_el x0, 0f, 1f, 0f
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0: ret
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1:
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/* Initialize Generic Timers */
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mrs x0, cnthctl_el2
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orr x0, x0, #0x3 /* Enable EL1 access to timers */
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr
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mrs x0, cntkctl_el1
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orr x0, x0, #0x3 /* Enable EL0 access to timers */
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msr cntkctl_el1, x0
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/* Initilize MPID/MPIDR registers */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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/* Disable coprocessor traps */
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
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msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
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/* Initialize HCR_EL2 */
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mov x0, #(1 << 31) /* 64bit EL1 */
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orr x0, x0, #(1 << 29) /* Disable HVC */
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msr hcr_el2, x0
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/* SCTLR_EL1 initialization */
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mov x0, #0x0800
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movk x0, #0x30d0, lsl #16
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msr sctlr_el1, x0
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/* Return to the EL1_SP1 mode from EL2 */
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mov x0, sp
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msr sp_el1, x0 /* Migrate SP */
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mrs x0, vbar_el2
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msr vbar_el1, x0 /* Migrate VBAR */
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mov x0, #0x3c5
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msr spsr_el2, x0 /* EL1_SP1 | D | A | I | F */
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msr elr_el2, lr
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eret
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ENDPROC(armv8_switch_to_el1)
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