mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
![Heiko Schocher](/assets/img/avatar_default.png)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz Board: aristaitenos I2C: ready DRAM: 1 GiB NAND: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lb07wv8 (800x480) - UART5 is console - MMC 0 and 1 - USB 0 and 1 - boot from mmc0 and spi nor flash - Splash screen support Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
25 lines
667 B
INI
25 lines
667 B
INI
/*
|
|
* Copyright (C) 2013 Boundary Devices
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
/* set the default clock gate to save power */
|
|
DATA 4, CCM_CCGR0, 0x00c03f3f
|
|
DATA 4, CCM_CCGR1, 0x0030fcff
|
|
DATA 4, CCM_CCGR2, 0x0fffcfc0
|
|
DATA 4, CCM_CCGR3, 0x3ff0300f
|
|
DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
|
|
DATA 4, CCM_CCGR5, 0x0f0000c3
|
|
DATA 4, CCM_CCGR6, 0x000003ff
|