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https://github.com/brain-hackers/u-boot-brain
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![Albert ARIBAUD](/assets/img/avatar_default.png)
Remove the last uses of symbol offsets in ARM U-Boot. Remove some needless uses of _TEXT_BASE. Remove all _TEXT_BASE definitions. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
362 lines
6.9 KiB
ArmAsm
362 lines
6.9 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM920 CPU-core
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <common.h>
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#include <config.h>
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start: b start_code
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (called from the ARM reset exception vector)
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*
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* do important init only if we don't start from memory!
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual start code
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*/
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start_code:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0xd3
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msr cpsr, r0
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#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
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/*
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* relocate exception table
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*/
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ldr r0, =_start
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ldr r1, =0x0
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mov r2, #16
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copyex:
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subs r2, r2, #1
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ldr r3, [r0], #4
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str r3, [r1], #4
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bne copyex
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#endif
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#ifdef CONFIG_S3C24X0
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/* turn off the watchdog */
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# if defined(CONFIG_S3C2400)
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# define pWTCON 0x15300000
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# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
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# define CLKDIVN 0x14800014 /* clock divisor register */
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#else
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# define pWTCON 0x53000000
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# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
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# define INTSUBMSK 0x4A00001C
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# define CLKDIVN 0x4C000014 /* clock divisor register */
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# endif
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ldr r0, =pWTCON
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mov r1, #0x0
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str r1, [r0]
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/*
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* mask all IRQs by setting all bits in the INTMR - default
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*/
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mov r1, #0xffffffff
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ldr r0, =INTMSK
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str r1, [r0]
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# if defined(CONFIG_S3C2410)
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ldr r1, =0x3ff
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ldr r0, =INTSUBMSK
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str r1, [r0]
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# endif
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/* FCLK:HCLK:PCLK = 1:2:4 */
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/* default FCLK is 120 MHz ! */
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ldr r0, =CLKDIVN
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mov r1, #3
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str r1, [r0]
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#endif /* CONFIG_S3C24X0 */
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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mov pc, lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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mov pc, lr
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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ldr r2, IRQ_STACK_START_IN
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ldmia r2, {r2 - r3} @ get pc, cpsr
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r7, sp, #S_PC
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stmdb r7, {sp, lr}^ @ Calling SP, LR
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str lr, [r7, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r7, #4] @ Save CPSR
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str r0, [r7, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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/* return & move spsr_svc into cpsr */
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subs pc, lr, #4
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13
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mov lr, pc
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movs pc, lr
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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