mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
2a5f7f2074
On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <asm/arch/tegra.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern unsigned long nvtboot_boot_x0;
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/*
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* A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
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*
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* We only support up to two banks since that's all the binary bootloader
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* ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G.
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* This is all a fairly safe assumption, since the L4T kernel makes the same
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* assumptions, so the bootloader is unlikely to change.
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*
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* This is written to before relocation, and hence cannot be in .bss, since
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* .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
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* forces this into .data and avoids this issue. This also has the nice side-
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* effect of the content being valid after relocation.
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*/
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static struct {
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u64 start;
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u64 size;
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} ram_banks[2] = {{1}};
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int dram_init(void)
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{
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unsigned int na, ns;
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const void *nvtboot_blob = (void *)nvtboot_boot_x0;
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int node, len, i;
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const u32 *prop;
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memset(ram_banks, 0, sizeof(ram_banks));
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na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
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ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
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node = fdt_path_offset(nvtboot_blob, "/memory");
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if (node < 0) {
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error("Can't find /memory node in nvtboot DTB");
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hang();
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}
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prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
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if (!prop) {
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error("Can't find /memory/reg property in nvtboot DTB");
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hang();
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}
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len /= (na + ns);
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if (len > ARRAY_SIZE(ram_banks))
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len = ARRAY_SIZE(ram_banks);
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gd->ram_size = 0;
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for (i = 0; i < len; i++) {
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ram_banks[i].start = of_read_number(prop, na);
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prop += na;
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ram_banks[i].size = of_read_number(prop, ns);
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prop += ns;
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gd->ram_size += ram_banks[i].size;
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}
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return 0;
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}
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extern unsigned long nvtboot_boot_x0;
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void dram_init_banksize(void)
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{
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int i;
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for (i = 0; i < 2; i++) {
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gd->bd->bi_dram[i].start = ram_banks[i].start;
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gd->bd->bi_dram[i].size = ram_banks[i].size;
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}
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return ram_banks[0].start + ram_banks[0].size;
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}
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