mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
983e37007d
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
106 lines
2.0 KiB
C
106 lines
2.0 KiB
C
/*
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* OMAP4 boot
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*
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* Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/omap_common.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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static u32 boot_devices[] = {
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_NONE,
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BOOT_DEVICE_XIPWAIT,
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};
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u32 omap_sys_boot_device(void)
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{
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u32 sys_boot;
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/* Grab the first 5 bits of the status register for SYS_BOOT. */
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sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
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if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
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return BOOT_DEVICE_NONE;
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return boot_devices[sys_boot];
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}
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int omap_reboot_mode(char *mode, unsigned int length)
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{
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unsigned int limit;
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unsigned int i;
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if (length < 2)
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return -1;
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if (!warm_reset())
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return -1;
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limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
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OMAP_REBOOT_REASON_SIZE;
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for (i = 0; i < (limit - 1); i++)
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mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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mode[i] = '\0';
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return 0;
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}
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int omap_reboot_mode_clear(void)
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{
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writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
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return 0;
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}
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int omap_reboot_mode_store(char *mode)
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{
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unsigned int i;
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for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
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writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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return 0;
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}
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