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https://github.com/brain-hackers/u-boot-brain
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b899fa3901
As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode This will fix the Linux kernel boot issue when use Lower address Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
265 lines
6.4 KiB
C
265 lines
6.4 KiB
C
/*
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* (C) Copyright 2013 Atmel Corporation
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* Josh Wu <josh.wu@atmel.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9x5_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <atmel_hlcdc.h>
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#include <atmel_mci.h>
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#include <netdev.h>
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_NAND_ATMEL
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static void at91sam9n12ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
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/* Configure databus */
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csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
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/* Configure IO drive */
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csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[3].mode);
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/* Configure RDY/BSY pin */
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at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
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/* Configure ENABLE pin for NandFlash */
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at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
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at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
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at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
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at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 480,
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.vl_row = 272,
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.vl_clk = 9000000,
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.vl_bpix = LCD_BPP,
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.vl_sync = 0,
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.vl_tft = 1,
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.vl_hsync_len = 5,
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.vl_left_margin = 8,
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.vl_right_margin = 43,
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.vl_vsync_len = 10,
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.vl_upper_margin = 4,
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.vl_lower_margin = 12,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
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}
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#ifdef CONFIG_LCD_INFO
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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int i;
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char temp[32];
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lcd_printf("%s\n", U_BOOT_VERSION);
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lcd_printf("ATMEL Corp\n");
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lcd_printf("at91@atmel.com\n");
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lcd_printf("%s CPU at %s MHz\n",
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ATMEL_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
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dram_size >> 20,
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nand_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < 2;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 0:
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at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
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break;
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case 1:
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at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
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break;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 0:
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at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
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break;
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case 1:
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at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
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break;
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}
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}
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#endif /* CONFIG_ATMEL_SPI */
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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int board_mmc_init(bd_t *bd)
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{
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at91_mci_hw_init();
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return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
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}
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#endif
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#ifdef CONFIG_KS8851_MLL
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void at91sam9n12ek_ks8851_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
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AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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/* Configure NCS2 PIN */
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at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
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}
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#endif
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int board_early_init_f(void)
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{
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/* Enable clocks for all PIOs */
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND_ATMEL
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at91sam9n12ek_nand_hw_init();
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_LCD
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at91_lcd_hw_init();
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#endif
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#ifdef CONFIG_KS8851_MLL
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at91sam9n12ek_ks8851_hw_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_KS8851_MLL
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int board_eth_init(bd_t *bis)
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{
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return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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