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According to De Morgan's Law[1]: !(A && B) = !A || !B !(A || B) = !A && !B There are 5 places in the code where we find: #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) and 4 places in the code where we find: #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) In words, the construct: !defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE on?" and the construct: defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE off?" Therefore !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) means: "the opposite of 'are they both off?'" in other words: "are either or both on?" and: (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) means: "are either or both on?" As a result, I've converted the 4 instances of '(!A || !B)' to '!(A && B)' for consistency. [1] https://en.wikipedia.org/wiki/De_Morgan%27s_laws Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
111 lines
2.2 KiB
C
111 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2004 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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static void cache_flush(void);
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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disable_interrupts ();
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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/* flush I/D-cache */
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cache_flush();
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return 0;
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}
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static void cache_flush(void)
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{
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unsigned long i = 0;
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/* clean entire data cache */
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
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/* invalidate both caches and flush btb */
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asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
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/* mem barrier to sync things */
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void invalidate_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
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}
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void flush_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#endif
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