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https://github.com/brain-hackers/u-boot-brain
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cac833a98c
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
146 lines
3.7 KiB
C
146 lines
3.7 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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u32 get_cpu_rev(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg = readl(&anatop->digprog);
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/* Read mx6 variant: quad, dual or solo */
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int system_rev = (reg >> 4) & 0xFF000;
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/* Read mx6 silicon revision */
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system_rev |= (reg & 0xFF) + 0x10;
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return system_rev;
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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void init_aips(void)
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{
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struct aipstz_regs *aips1, *aips2;
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips1->mprot0);
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writel(0x77777777, &aips1->mprot1);
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writel(0x77777777, &aips2->mprot0);
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writel(0x77777777, &aips2->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips1->opacr0);
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writel(0x00000000, &aips1->opacr1);
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writel(0x00000000, &aips1->opacr2);
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writel(0x00000000, &aips1->opacr3);
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writel(0x00000000, &aips1->opacr4);
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writel(0x00000000, &aips2->opacr0);
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writel(0x00000000, &aips2->opacr1);
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writel(0x00000000, &aips2->opacr2);
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr4);
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}
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/*
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* Set the VDDSOC
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*
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* Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
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* them to the specified millivolt level.
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* Possible values are from 0.725V to 1.450V in steps of
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* 0.025V (25mV).
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*/
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void set_vddsoc(u32 mv)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 val, reg = readl(&anatop->reg_core);
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if (mv < 725)
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val = 0x00; /* Power gated off */
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else if (mv > 1450)
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val = 0x1F; /* Power FET switched full on. No regulation */
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else
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val = (mv - 700) / 25;
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/*
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* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
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* and set them to the calculated value (0.7V + val * 0.25V)
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*/
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reg = (reg & ~(0x1F << 18)) | (val << 18);
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writel(reg, &anatop->reg_core);
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}
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int arch_cpu_init(void)
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{
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init_aips();
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set_vddsoc(1200); /* Set VDDSOC to 1.2V */
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return 0;
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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u32 value = readl(&fuse->mac_addr_high);
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mac[0] = (value >> 8);
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mac[1] = value ;
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value = readl(&fuse->mac_addr_low);
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mac[2] = value >> 24 ;
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mac[3] = value >> 16 ;
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mac[4] = value >> 8 ;
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mac[5] = value ;
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}
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#endif
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