mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
/*
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* (C) Copyright 2005
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* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/processor.h>
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int checkboard(void)
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{
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puts ("Board: KVME080\n");
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return 0;
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}
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unsigned long setdram(int m, int row, int col, int bank)
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{
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int i;
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unsigned long start, end;
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uint32_t mccr1;
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uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
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uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
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uint8_t mber = 0;
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CONFIG_READ_WORD(MCCR1, mccr1);
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mccr1 &= 0xffff0000;
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start = CFG_SDRAM_BASE;
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end = start + (1 << (col + row + 3) ) * bank - 1;
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for (i = 0; i < m; i++) {
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mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
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if (i < 4) {
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msar1 |= ((start >> 20) & 0xff) << i * 8;
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emsar1 |= ((start >> 28) & 0xff) << i * 8;
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mear1 |= ((end >> 20) & 0xff) << i * 8;
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emear1 |= ((end >> 28) & 0xff) << i * 8;
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} else {
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msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
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emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
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mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
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emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
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}
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mber |= 1 << i;
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start += (1 << (col + row + 3) ) * bank;
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end += (1 << (col + row + 3) ) * bank;
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}
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for (; i < 8; i++) {
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if (i < 4) {
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msar1 |= 0xff << i * 8;
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emsar1 |= 0x30 << i * 8;
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mear1 |= 0xff << i * 8;
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emear1 |= 0x30 << i * 8;
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} else {
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msar2 |= 0xff << (i-4) * 8;
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emsar2 |= 0x30 << (i-4) * 8;
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mear2 |= 0xff << (i-4) * 8;
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emear2 |= 0x30 << (i-4) * 8;
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}
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}
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CONFIG_WRITE_WORD(MCCR1, mccr1);
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CONFIG_WRITE_WORD(MSAR1, msar1);
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CONFIG_WRITE_WORD(EMSAR1, emsar1);
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CONFIG_WRITE_WORD(MEAR1, mear1);
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CONFIG_WRITE_WORD(EMEAR1, emear1);
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CONFIG_WRITE_WORD(MSAR2, msar2);
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CONFIG_WRITE_WORD(EMSAR2, emsar2);
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CONFIG_WRITE_WORD(MEAR2, mear2);
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CONFIG_WRITE_WORD(EMEAR2, emear2);
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CONFIG_WRITE_BYTE(MBER, mber);
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return (1 << (col + row + 3) ) * bank * m;
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}
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long int initdram(int board_type)
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{
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unsigned int msr;
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long int size = 0;
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msr = mfmsr();
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mtmsr(msr & ~(MSR_IR | MSR_DR));
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mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
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mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
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mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
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mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
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mtmsr(msr);
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if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
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size = 0x20000000; /* 512MB */
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else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
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size = 0x10000000; /* 256MB */
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else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
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size = 0x10000000; /* 256MB */
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else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
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size = 0x08000000; /* 128MB */
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else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
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size = 0x08000000; /* 128MB */
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else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
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size = 0x04000000; /* 64MB */
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msr = mfmsr();
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mtmsr(msr & ~(MSR_IR | MSR_DR));
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mtspr(IBAT2L, CFG_IBAT2L);
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mtspr(IBAT2U, CFG_IBAT2U);
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mtspr(DBAT2L, CFG_DBAT2L);
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mtspr(DBAT2U, CFG_DBAT2U);
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mtmsr(msr);
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return size;
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}
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struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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int board_early_init_f(void)
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{
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*(volatile unsigned char *)(0xff080120) = 0xfb;
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return 0;
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}
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int board_early_init_r(void)
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{
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unsigned int msr;
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CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
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CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
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CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
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msr = mfmsr();
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mtmsr(msr & ~(MSR_IR | MSR_DR));
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mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
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mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
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mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
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mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
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mtmsr(msr);
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return 0;
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}
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extern int multiverse_init(void);
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int misc_init_r(void)
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{
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multiverse_init();
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return 0;
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}
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void *nvram_read(void *dest, const long src, size_t count)
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{
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volatile uchar *d = (volatile uchar*) dest;
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volatile uchar *s = (volatile uchar*) src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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return dest;
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}
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void nvram_write(long dest, const void *src, size_t count)
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{
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volatile uchar *d = (volatile uchar*)dest;
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volatile uchar *s = (volatile uchar*)src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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}
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