mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
227 lines
5.2 KiB
C
227 lines
5.2 KiB
C
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2005
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - not compressed, generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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int filesize = sizeof(fpgadata);
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000);
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/*
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* Setup GPIO pins
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*/
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
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CFG_FPGA_DONE | \
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CFG_XEREADY | \
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CFG_NONMONARCH | \
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CFG_REV1_2) << 5));
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if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
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/* rev 1.2 boards */
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
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CFG_SELF_RST) << 5));
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}
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out32(GPIO0_OR, 0);
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out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
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/* - check if rev1_2 is low, then:
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* - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
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*/
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
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return (0);
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}
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ushort pmc405_pci_subsys_deviceid(void)
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{
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ulong val;
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val = in32(GPIO0_IR);
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if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
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if (val & CFG_NONMONARCH) { /* monarch# signal */
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return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
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}
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return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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ulong val;
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming PMC405");
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} else {
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puts(str);
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}
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val = in32(GPIO0_IR);
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if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
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puts(" rev1.2 (");
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if (val & CFG_NONMONARCH) { /* monarch# signal */
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puts("non-");
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}
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puts("monarch)");
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} else {
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puts(" <=rev1.1");
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}
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr;
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volatile uchar *ptr;
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volatile uchar val;
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int i;
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addr = simple_strtol (argv[1], NULL, 16) + 0x16;
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i = 0;
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for (;;) {
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ptr = (uchar *)addr;
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for (i=0; i<8; i++) {
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*ptr = i;
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val = *ptr;
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if (val != i) {
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printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
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return 0;
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}
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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ptr++;
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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cantest, 3, 1, do_cantest,
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"cantest - Test CAN controller",
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NULL
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);
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