337 lines
8.4 KiB
C
337 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <log.h>
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#include <tee.h>
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#include <asm/arch/sys_proto.h>
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <linux/io.h>
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#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
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#define ETZPC_DECPROT_NB 6
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#define DECPROT_MASK 0x03
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#define NB_PROT_PER_REG 0x10
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#define DECPROT_NB_BITS 2
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#define DECPROT_SECURED 0x00
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#define DECPROT_WRITE_SECURE 0x01
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#define DECPROT_MCU_ISOLATION 0x02
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#define DECPROT_NON_SECURED 0x03
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#define ETZPC_RESERVED 0xffffffff
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#define STM32_FDCAN_BASE 0x4400e000
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#define STM32_CRYP2_BASE 0x4c005000
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#define STM32_CRYP1_BASE 0x54001000
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#define STM32_GPU_BASE 0x59000000
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#define STM32_DSI_BASE 0x5a000000
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static const u32 stm32mp1_ip_addr[] = {
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0x5c008000, /* 00 stgenc */
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0x54000000, /* 01 bkpsram */
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0x5c003000, /* 02 iwdg1 */
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0x5c000000, /* 03 usart1 */
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0x5c001000, /* 04 spi6 */
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0x5c002000, /* 05 i2c4 */
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ETZPC_RESERVED, /* 06 reserved */
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0x54003000, /* 07 rng1 */
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0x54002000, /* 08 hash1 */
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STM32_CRYP1_BASE, /* 09 cryp1 */
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0x5a003000, /* 0A ddrctrl */
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0x5a004000, /* 0B ddrphyc */
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0x5c009000, /* 0C i2c6 */
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ETZPC_RESERVED, /* 0D reserved */
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ETZPC_RESERVED, /* 0E reserved */
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ETZPC_RESERVED, /* 0F reserved */
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0x40000000, /* 10 tim2 */
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0x40001000, /* 11 tim3 */
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0x40002000, /* 12 tim4 */
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0x40003000, /* 13 tim5 */
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0x40004000, /* 14 tim6 */
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0x40005000, /* 15 tim7 */
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0x40006000, /* 16 tim12 */
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0x40007000, /* 17 tim13 */
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0x40008000, /* 18 tim14 */
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0x40009000, /* 19 lptim1 */
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0x4000a000, /* 1A wwdg1 */
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0x4000b000, /* 1B spi2 */
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0x4000c000, /* 1C spi3 */
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0x4000d000, /* 1D spdifrx */
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0x4000e000, /* 1E usart2 */
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0x4000f000, /* 1F usart3 */
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0x40010000, /* 20 uart4 */
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0x40011000, /* 21 uart5 */
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0x40012000, /* 22 i2c1 */
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0x40013000, /* 23 i2c2 */
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0x40014000, /* 24 i2c3 */
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0x40015000, /* 25 i2c5 */
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0x40016000, /* 26 cec */
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0x40017000, /* 27 dac */
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0x40018000, /* 28 uart7 */
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0x40019000, /* 29 uart8 */
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ETZPC_RESERVED, /* 2A reserved */
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ETZPC_RESERVED, /* 2B reserved */
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0x4001c000, /* 2C mdios */
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ETZPC_RESERVED, /* 2D reserved */
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ETZPC_RESERVED, /* 2E reserved */
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ETZPC_RESERVED, /* 2F reserved */
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0x44000000, /* 30 tim1 */
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0x44001000, /* 31 tim8 */
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ETZPC_RESERVED, /* 32 reserved */
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0x44003000, /* 33 usart6 */
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0x44004000, /* 34 spi1 */
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0x44005000, /* 35 spi4 */
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0x44006000, /* 36 tim15 */
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0x44007000, /* 37 tim16 */
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0x44008000, /* 38 tim17 */
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0x44009000, /* 39 spi5 */
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0x4400a000, /* 3A sai1 */
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0x4400b000, /* 3B sai2 */
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0x4400c000, /* 3C sai3 */
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0x4400d000, /* 3D dfsdm */
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STM32_FDCAN_BASE, /* 3E tt_fdcan */
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ETZPC_RESERVED, /* 3F reserved */
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0x50021000, /* 40 lptim2 */
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0x50022000, /* 41 lptim3 */
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0x50023000, /* 42 lptim4 */
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0x50024000, /* 43 lptim5 */
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0x50027000, /* 44 sai4 */
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0x50025000, /* 45 vrefbuf */
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0x4c006000, /* 46 dcmi */
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0x4c004000, /* 47 crc2 */
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0x48003000, /* 48 adc */
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0x4c002000, /* 49 hash2 */
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0x4c003000, /* 4A rng2 */
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STM32_CRYP2_BASE, /* 4B cryp2 */
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ETZPC_RESERVED, /* 4C reserved */
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ETZPC_RESERVED, /* 4D reserved */
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ETZPC_RESERVED, /* 4E reserved */
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ETZPC_RESERVED, /* 4F reserved */
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ETZPC_RESERVED, /* 50 sram1 */
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ETZPC_RESERVED, /* 51 sram2 */
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ETZPC_RESERVED, /* 52 sram3 */
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ETZPC_RESERVED, /* 53 sram4 */
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ETZPC_RESERVED, /* 54 retram */
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0x49000000, /* 55 otg */
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0x48004000, /* 56 sdmmc3 */
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0x48005000, /* 57 dlybsd3 */
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0x48000000, /* 58 dma1 */
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0x48001000, /* 59 dma2 */
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0x48002000, /* 5A dmamux */
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0x58002000, /* 5B fmc */
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0x58003000, /* 5C qspi */
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0x58004000, /* 5D dlybq */
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0x5800a000, /* 5E eth */
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ETZPC_RESERVED, /* 5F reserved */
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};
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/* fdt helper */
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static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
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{
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int node;
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fdt_addr_t regs;
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for (node = fdt_first_subnode(fdt, offset);
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node >= 0;
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node = fdt_next_subnode(fdt, node)) {
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regs = fdtdec_get_addr(fdt, node, "reg");
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if (addr == regs) {
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if (fdtdec_get_is_enabled(fdt, node)) {
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fdt_status_disabled(fdt, node);
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return true;
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}
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return false;
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}
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}
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return false;
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}
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static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
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{
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const u32 *array;
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int array_size, i;
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int offset, shift;
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u32 addr, status, decprot[ETZPC_DECPROT_NB];
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array = stm32mp1_ip_addr;
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array_size = ARRAY_SIZE(stm32mp1_ip_addr);
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for (i = 0; i < ETZPC_DECPROT_NB; i++)
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decprot[i] = readl(ETZPC_DECPROT(i));
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for (i = 0; i < array_size; i++) {
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offset = i / NB_PROT_PER_REG;
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shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
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status = (decprot[offset] >> shift) & DECPROT_MASK;
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addr = array[i];
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debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
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if (addr == ETZPC_RESERVED ||
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status == DECPROT_NON_SECURED)
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continue;
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if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
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printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
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addr, i, status);
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}
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return 0;
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}
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/* deactivate all the cpu except core 0 */
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static void stm32_fdt_fixup_cpu(void *blob, char *name)
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{
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int off;
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u32 reg;
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off = fdt_path_offset(blob, "/cpus");
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if (off < 0) {
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printf("%s: couldn't find /cpus node\n", __func__);
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return;
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}
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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reg = fdtdec_get_addr(blob, off, "reg");
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if (reg != 0) {
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fdt_del_node(blob, off);
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printf("FDT: cpu %d node remove for %s\n", reg, name);
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/* after delete we can't trust the offsets anymore */
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off = -1;
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}
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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}
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static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
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const char *string, const char *name)
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{
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if (fdt_disable_subnode_by_address(fdt, offset, addr))
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printf("FDT: %s@%08x node disabled for %s\n",
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string, addr, name);
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}
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static void stm32_fdt_disable_optee(void *blob)
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{
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int off, node;
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/* Delete "optee" firmware node */
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off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
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if (off >= 0 && fdtdec_get_is_enabled(blob, off))
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fdt_del_node(blob, off);
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/* Delete "optee@..." reserved-memory node */
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off = fdt_path_offset(blob, "/reserved-memory/");
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if (off < 0)
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return;
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for (node = fdt_first_subnode(blob, off);
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node >= 0;
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node = fdt_next_subnode(blob, node)) {
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if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
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continue;
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if (fdt_del_node(blob, node))
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printf("Failed to remove optee reserved-memory node\n");
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}
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}
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/*
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* This function is called right before the kernel is booted. "blob" is the
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* device tree that will be passed to the kernel.
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*/
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int ft_system_setup(void *blob, struct bd_info *bd)
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{
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int ret = 0;
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int soc;
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u32 pkg, cpu;
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char name[SOC_NAME_SIZE];
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soc = fdt_path_offset(blob, "/soc");
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if (soc < 0)
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return soc;
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if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
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ret = stm32_fdt_fixup_etzpc(blob, soc);
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if (ret)
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return ret;
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}
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/* MPUs Part Numbers and name*/
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cpu = get_cpu_type();
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get_soc_name(name);
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switch (cpu) {
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case CPU_STM32MP151Fxx:
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case CPU_STM32MP151Dxx:
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case CPU_STM32MP151Cxx:
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case CPU_STM32MP151Axx:
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stm32_fdt_fixup_cpu(blob, name);
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/* after cpu delete we can't trust the soc offsets anymore */
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soc = fdt_path_offset(blob, "/soc");
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stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
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/* fall through */
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case CPU_STM32MP153Fxx:
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case CPU_STM32MP153Dxx:
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case CPU_STM32MP153Cxx:
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case CPU_STM32MP153Axx:
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stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
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stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
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break;
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default:
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break;
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}
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switch (cpu) {
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case CPU_STM32MP157Dxx:
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case CPU_STM32MP157Axx:
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case CPU_STM32MP153Dxx:
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case CPU_STM32MP153Axx:
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case CPU_STM32MP151Dxx:
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case CPU_STM32MP151Axx:
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stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
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stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
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break;
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default:
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break;
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}
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switch (get_cpu_package()) {
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case PKG_AA_LBGA448:
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pkg = STM32MP_PKG_AA;
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break;
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case PKG_AB_LBGA354:
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pkg = STM32MP_PKG_AB;
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break;
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case PKG_AC_TFBGA361:
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pkg = STM32MP_PKG_AC;
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break;
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case PKG_AD_TFBGA257:
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pkg = STM32MP_PKG_AD;
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break;
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default:
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pkg = 0;
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break;
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}
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if (pkg) {
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do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
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"st,package", pkg, false);
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do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
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"st,package", pkg, false);
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}
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if (!CONFIG_IS_ENABLED(OPTEE) ||
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!tee_find_device(NULL, NULL, NULL, NULL))
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stm32_fdt_disable_optee(blob);
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return ret;
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}
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