mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 07:43:22 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
378 lines
7.5 KiB
C
378 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/mach-imx/sys_proto.h>
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#include <netdev.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#ifdef CONFIG_FSL_ESDHC
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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static char soc_type[] = "xx0";
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 reg;
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reg = readl(&ccm->ccgr6);
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if (enable)
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reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
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else
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reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
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writel(reg, &ccm->ccgr6);
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}
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#endif
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static u32 get_mcu_main_clk(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 ccm_ccsr, ccm_cacrr, armclk_div;
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u32 sysclk_sel, pll_pfd_sel = 0;
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u32 freq = 0;
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ccm_ccsr = readl(&ccm->ccsr);
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sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
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sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
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ccm_cacrr = readl(&ccm->cacrr);
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armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
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armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
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armclk_div += 1;
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switch (sysclk_sel) {
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case 0:
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freq = FASE_CLK_FREQ;
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break;
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case 1:
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freq = SLOW_CLK_FREQ;
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break;
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case 2:
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pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
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pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
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if (pll_pfd_sel == 0)
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freq = PLL2_MAIN_FREQ;
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else if (pll_pfd_sel == 1)
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freq = PLL2_PFD1_FREQ;
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else if (pll_pfd_sel == 2)
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freq = PLL2_PFD2_FREQ;
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else if (pll_pfd_sel == 3)
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freq = PLL2_PFD3_FREQ;
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else if (pll_pfd_sel == 4)
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freq = PLL2_PFD4_FREQ;
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break;
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case 3:
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freq = PLL2_MAIN_FREQ;
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break;
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case 4:
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pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
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pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
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if (pll_pfd_sel == 0)
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freq = PLL1_MAIN_FREQ;
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else if (pll_pfd_sel == 1)
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freq = PLL1_PFD1_FREQ;
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else if (pll_pfd_sel == 2)
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freq = PLL1_PFD2_FREQ;
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else if (pll_pfd_sel == 3)
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freq = PLL1_PFD3_FREQ;
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else if (pll_pfd_sel == 4)
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freq = PLL1_PFD4_FREQ;
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break;
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case 5:
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freq = PLL3_MAIN_FREQ;
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break;
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default:
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printf("unsupported system clock select\n");
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}
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return freq / armclk_div;
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}
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static u32 get_bus_clk(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 ccm_cacrr, busclk_div;
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ccm_cacrr = readl(&ccm->cacrr);
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busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
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busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
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busclk_div += 1;
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return get_mcu_main_clk() / busclk_div;
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}
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static u32 get_ipg_clk(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 ccm_cacrr, ipgclk_div;
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ccm_cacrr = readl(&ccm->cacrr);
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ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
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ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
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ipgclk_div += 1;
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return get_bus_clk() / ipgclk_div;
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}
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static u32 get_uart_clk(void)
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{
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return get_ipg_clk();
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}
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static u32 get_sdhc_clk(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
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u32 freq = 0;
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ccm_cscmr1 = readl(&ccm->cscmr1);
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sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
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sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
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ccm_cscdr2 = readl(&ccm->cscdr2);
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sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
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sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
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sdhc_clk_div += 1;
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switch (sdhc_clk_sel) {
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case 0:
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freq = PLL3_MAIN_FREQ;
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break;
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case 1:
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freq = PLL3_PFD3_FREQ;
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break;
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case 2:
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freq = PLL1_PFD3_FREQ;
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break;
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case 3:
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freq = get_bus_clk();
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break;
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}
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return freq / sdhc_clk_div;
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}
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u32 get_fec_clk(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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u32 ccm_cscmr2, rmii_clk_sel;
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u32 freq = 0;
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ccm_cscmr2 = readl(&ccm->cscmr2);
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rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
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rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
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switch (rmii_clk_sel) {
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case 0:
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freq = ENET_EXTERNAL_CLK;
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break;
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case 1:
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freq = AUDIO_EXTERNAL_CLK;
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break;
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case 2:
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freq = PLL5_MAIN_FREQ;
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break;
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case 3:
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freq = PLL5_MAIN_FREQ / 2;
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break;
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}
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return freq;
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}
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static u32 get_i2c_clk(void)
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{
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return get_ipg_clk();
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}
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static u32 get_dspi_clk(void)
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{
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return get_ipg_clk();
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}
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u32 get_lpuart_clk(void)
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{
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return get_uart_clk();
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_BUS_CLK:
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return get_bus_clk();
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_UART_CLK:
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return get_uart_clk();
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case MXC_ESDHC_CLK:
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return get_sdhc_clk();
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case MXC_FEC_CLK:
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return get_fec_clk();
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case MXC_I2C_CLK:
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return get_i2c_clk();
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case MXC_DSPI_CLK:
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return get_dspi_clk();
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default:
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break;
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}
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return -1;
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}
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/* Dump some core clocks */
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int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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printf("\n");
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printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
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printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
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"display clocks",
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""
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);
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#ifdef CONFIG_FEC_MXC
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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u32 value = readl(&fuse->mac_addr0);
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mac[0] = (value >> 8);
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mac[1] = value;
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value = readl(&fuse->mac_addr1);
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mac[2] = value >> 24;
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mac[3] = value >> 16;
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mac[4] = value >> 8;
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mac[5] = value;
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}
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#endif
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u32 get_cpu_rev(void)
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{
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return MXC_CPU_VF610 << 12;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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static char *get_reset_cause(void)
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{
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u32 cause;
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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cause = readl(&src_regs->srsr);
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writel(cause, &src_regs->srsr);
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if (cause & SRC_SRSR_POR_RST)
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return "POWER ON RESET";
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else if (cause & SRC_SRSR_WDOG_A5)
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return "WDOG A5";
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else if (cause & SRC_SRSR_WDOG_M4)
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return "WDOG M4";
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else if (cause & SRC_SRSR_JTAG_RST)
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return "JTAG HIGH-Z";
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else if (cause & SRC_SRSR_SW_RST)
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return "SW RESET";
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else if (cause & SRC_SRSR_RESETB)
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return "EXTERNAL RESET";
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else
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return "unknown reset";
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}
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int print_cpuinfo(void)
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{
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printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
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soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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int arch_cpu_init(void)
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{
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struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
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soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
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soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
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return 0;
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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char soc[6];
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strcpy(soc, "vf");
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strcat(soc, soc_type);
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env_set("soc", soc);
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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#endif
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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enum dcache_option option = DCACHE_WRITETHROUGH;
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#else
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enum dcache_option option = DCACHE_WRITEBACK;
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#endif
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dcache_enable();
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icache_enable();
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/* Enable caching on OCRAM */
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mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
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}
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#endif
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