mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
89f44bb0ce
This patch adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. By default, ECC will only be enabled if RMW is supported in the DDR EMIF controller. The entire DDR memory will be scrubbed to zero using an EDMA channel after ECC is enabled and before u-boot is re-located to DDR memory. An ecc_test environment variable is added for ECC testing. If ecc_test is set to 0, a detection of 2-bit error will reset the device, if ecc_test is set to 1, 2-bit error detection will not reset the device, user can still boot the kernel to check the ECC error handling in kernel. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
105 lines
2.5 KiB
C
105 lines
2.5 KiB
C
/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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#include <asm/arch/hardware.h>
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static int ddr3_size;
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struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
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struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
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void ddr3_init(void)
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{
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char dimm_name[32];
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ddr3_get_dimm_params(dimm_name);
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printf("Detected SO-DIMM [%s]\n", dimm_name);
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if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
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init_pll(&ddr3a_400);
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if (cpu_revision() > 0) {
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if (cpu_revision() > 1) {
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/* PG 2.0 */
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/* Reset DDR3A PHY after PLL enabled */
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ddr3_reset_ddrphy();
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ddr3phy_1600_8g.zq0cr1 |= 0x10000;
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ddr3phy_1600_8g.zq1cr1 |= 0x10000;
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ddr3phy_1600_8g.zq2cr1 |= 0x10000;
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
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&ddr3phy_1600_8g);
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} else {
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/* PG 1.1 */
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
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&ddr3phy_1600_8g);
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}
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
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&ddr3_1600_8g);
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printf("DRAM: Capacity 8 GiB (includes reported below)\n");
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ddr3_size = 8;
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} else {
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
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ddr3_1600_8g.sdcfg |= 0x1000;
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
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&ddr3_1600_8g);
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printf("DRAM: Capacity 4 GiB (includes reported below)\n");
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ddr3_size = 4;
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}
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} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
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init_pll(&ddr3a_333);
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if (cpu_revision() > 0) {
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if (cpu_revision() > 1) {
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/* PG 2.0 */
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/* Reset DDR3A PHY after PLL enabled */
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ddr3_reset_ddrphy();
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ddr3phy_1333_2g.zq0cr1 |= 0x10000;
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ddr3phy_1333_2g.zq1cr1 |= 0x10000;
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ddr3phy_1333_2g.zq2cr1 |= 0x10000;
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
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&ddr3phy_1333_2g);
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} else {
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/* PG 1.1 */
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
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&ddr3phy_1333_2g);
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}
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
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&ddr3_1333_2g);
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ddr3_size = 2;
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printf("DRAM: 2 GiB");
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} else {
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
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ddr3_1333_2g.sdcfg |= 0x1000;
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
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&ddr3_1333_2g);
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ddr3_size = 1;
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printf("DRAM: 1 GiB");
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}
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} else {
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printf("Unknown SO-DIMM. Cannot configure DDR3\n");
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while (1)
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;
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}
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/* Apply the workaround for PG 1.0 and 1.1 Silicons */
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if (cpu_revision() <= 1)
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ddr3_err_reset_workaround();
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}
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/**
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* ddr3_get_size - return ddr3 size in GiB
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*/
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int ddr3_get_size(void)
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{
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return ddr3_size;
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}
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