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https://github.com/brain-hackers/u-boot-brain
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660673af4f
LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
19 lines
393 B
C
19 lines
393 B
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/ls102xa_stream_id.h>
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void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
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{
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uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
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int i;
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for (i = 0; i < num; i++)
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out_be32(scfg + id[i].offset, id[i].stream_id);
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}
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