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70ad375ee4
This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
43 lines
898 B
C
43 lines
898 B
C
/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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void pin_mux_usb(void)
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{
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/*
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* USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
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* in the current device tree.
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*/
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pinmux_tristate_disable(PMUX_PINGRP_UAC);
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}
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void pin_mux_spi(void)
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{
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funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
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}
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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void pin_mux_mmc(void)
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{
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funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
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funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
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/* For CD GPIO PP1 */
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pinmux_tristate_disable(PMUX_PINGRP_DAP3);
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}
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