Michal Simek 39523bef29 zynq: slcr: Wait 100ms till clk is properly setup ... If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>		2013-08-12 08:59:55 +02:00
..
cpu.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
ddrc.c	zynq: Add new ddrc driver for ECC support	2013-08-12 08:59:55 +02:00
Makefile	zynq: Add new ddrc driver for ECC support	2013-08-12 08:59:55 +02:00
slcr.c	zynq: slcr: Wait 100ms till clk is properly setup	2013-08-12 08:59:55 +02:00
timer.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00