mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-03 03:13:21 +09:00
d491dc09e4
This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
26 lines
854 B
C
26 lines
854 B
C
#ifndef _TEGRA_XUSB_PADCTL_H_
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#define _TEGRA_XUSB_PADCTL_H_
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struct tegra_xusb_phy;
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/**
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* tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
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* @type: the type of PHY to obtain
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*
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* The type of PHY varies between SoC generations. Typically there are XUSB,
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* PCIe and SATA PHYs, though not all generations support all of them. The
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* value of type can usually be directly parsed from a device tree.
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*
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* Return: a pointer to the PHY or NULL if no such PHY exists
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*/
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
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void tegra_xusb_padctl_init(void);
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void tegra_xusb_padctl_exit(void);
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
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#endif
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