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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
191 lines
3.2 KiB
C
191 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*/
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#ifndef __ASM_ARCH_DDR_RK3368_H__
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#define __ASM_ARCH_DDR_RK3368_H__
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/*
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* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
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* in a few details. Most notably, it has an additional field to track
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* tREFI in controller cycles (i.e. trefi_mem_ddr3).
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*/
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struct rk3368_ddr_pctl {
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u32 scfg;
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[12];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 cmdtstaten;
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u32 reserved1[3];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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u32 mstat;
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u32 lpddr2zqcfg;
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u32 reserved3;
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u32 dtupdes;
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u32 dtuna;
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u32 dtune;
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u32 dtuprd0;
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u32 dtuprd1;
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[3];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 trefi_mem_ddr3;
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u32 reserved5[45];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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u32 dtuectl;
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u32 dtuwd0;
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u32 dtuwd1;
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u32 dtuwd2;
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u32 dtuwd3;
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u32 dtuwdm;
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u32 dturd0;
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u32 dturd1;
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u32 dturd2;
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u32 dturd3;
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u32 dtulfsrwd;
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u32 dtulfsrrd;
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u32 dtueaf;
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u32 dfitctrldelay;
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u32 dfiodtcfg;
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u32 dfiodtcfg1;
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u32 dfiodtrankmap;
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u32 dfitphywrdata;
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u32 dfitphywrlat;
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u32 reserved7[2];
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[2];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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u32 dfitphyupdtype3;
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u32 dfitctrlupdmin;
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u32 dfitctrlupdmax;
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u32 dfitctrlupddly;
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u32 reserved9;
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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u32 dfitrrdlvlen;
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u32 dfitrrdlvlgateen;
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u32 dfiststat0;
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u32 dfistcfg0;
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u32 dfistcfg1;
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u32 reserved11;
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u32 dfitdramclken;
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u32 dfitdramclkdis;
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[3];
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u32 dfilpcfg0;
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u32 reserved13[3];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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u32 dfitrrdlvlresp0;
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u32 dfitrrdlvlresp1;
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u32 dfitrrdlvlresp2;
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u32 dfitrwrlvldelay0;
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u32 dfitrwrlvldelay1;
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u32 dfitrwrlvldelay2;
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u32 dfitrrdlvldelay0;
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u32 dfitrrdlvldelay1;
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u32 dfitrrdlvldelay2;
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u32 dfitrrdlvlgatedelay0;
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[46];
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u32 ipvr;
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u32 iptr;
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};
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check_member(rk3368_ddr_pctl, iptr, 0x03fc);
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struct rk3368_ddrphy {
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u32 reg[0x100];
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};
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check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
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struct rk3368_msch {
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u32 coreid;
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u32 revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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u32 reserved1[8];
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u32 activate;
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u32 devtodev;
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};
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check_member(rk3368_msch, devtodev, 0x003c);
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/* GRF_SOC_CON0 */
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enum {
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NOC_RSP_ERR_STALL = BIT(9),
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MOBILE_DDR_SEL = BIT(4),
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DDR0_16BIT_EN = BIT(3),
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MSCH0_MAINDDR3_DDR3 = BIT(2),
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MSCH0_MAINPARTIALPOP = BIT(1),
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UPCTL_C_ACTIVE = BIT(0),
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};
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#endif
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