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https://github.com/brain-hackers/u-boot-brain
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f0e8e8944d
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/imx-common/regs-common.h>
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#include "../arch-imx/cpu.h"
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#define soc_rev() (get_cpu_rev() & 0xFF)
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#define is_soc_rev(rev) (soc_rev() - rev)
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u32 get_nr_cpus(void);
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u32 get_cpu_rev(void);
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u32 get_cpu_speed_grade_hz(void);
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12)&0xff)
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/* both macros return/take MXC_CPU_ constants */
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#define get_cpu_type() (cpu_type(get_cpu_rev()))
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#define is_cpu_type(cpu) (get_cpu_type() == cpu)
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const char *get_imx_type(u32 imxtype);
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unsigned imx_ddr_size(void);
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void set_chipselect_size(int const);
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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#endif
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