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https://github.com/brain-hackers/u-boot-brain
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78c5a18087
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit. In slow-exit mode the DLL is off but in some quiescent state that makes it easy to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK). In fast-exist mode the DLL is maintained such that it is ready again in about 3tCK. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
356 lines
8.3 KiB
C
356 lines
8.3 KiB
C
/*
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* Copyright (C) 2013 Boundary Devices Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6_DDR_H__
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#define __ASM_ARCH_MX6_DDR_H__
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_MX6Q
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#include "mx6q-ddr.h"
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#else
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#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
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#include "mx6dl-ddr.h"
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#else
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#ifdef CONFIG_MX6SX
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#include "mx6sx-ddr.h"
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#else
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#error "Please select cpu"
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#endif /* CONFIG_MX6SX */
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#endif /* CONFIG_MX6DL or CONFIG_MX6S */
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#endif /* CONFIG_MX6Q */
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#else
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/* MMDC P0/P1 Registers */
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struct mmdc_p_regs {
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u32 mdctl;
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u32 mdpdc;
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u32 mdotc;
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u32 mdcfg0;
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u32 mdcfg1;
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u32 mdcfg2;
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u32 mdmisc;
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u32 mdscr;
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u32 mdref;
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u32 res1[2];
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u32 mdrwd;
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u32 mdor;
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u32 res2[3];
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u32 mdasp;
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u32 res3[240];
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u32 mapsr;
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u32 res4[254];
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u32 mpzqhwctrl;
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u32 res5[2];
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u32 mpwldectrl0;
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u32 mpwldectrl1;
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u32 res6;
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u32 mpodtctrl;
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u32 mprddqby0dl;
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u32 mprddqby1dl;
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u32 mprddqby2dl;
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u32 mprddqby3dl;
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u32 res7[4];
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u32 mpdgctrl0;
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u32 mpdgctrl1;
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u32 res8;
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u32 mprddlctl;
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u32 res9;
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u32 mpwrdlctl;
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u32 res10[25];
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u32 mpmur0;
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};
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#define MX6SX_IOM_DDR_BASE 0x020e0200
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struct mx6sx_iomux_ddr_regs {
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u32 res1[59];
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u32 dram_dqm0;
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u32 dram_dqm1;
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u32 dram_dqm2;
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u32 dram_dqm3;
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u32 dram_ras;
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u32 dram_cas;
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u32 res2[2];
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u32 dram_sdwe_b;
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u32 dram_odt0;
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u32 dram_odt1;
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u32 dram_sdba0;
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u32 dram_sdba1;
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u32 dram_sdba2;
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u32 dram_sdcke0;
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u32 dram_sdcke1;
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u32 dram_sdclk_0;
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u32 dram_sdqs0;
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u32 dram_sdqs1;
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u32 dram_sdqs2;
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u32 dram_sdqs3;
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u32 dram_reset;
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};
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#define MX6SX_IOM_GRP_BASE 0x020e0500
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struct mx6sx_iomux_grp_regs {
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u32 res1[61];
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u32 grp_addds;
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u32 grp_ddrmode_ctl;
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u32 grp_ddrpke;
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u32 grp_ddrpk;
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u32 grp_ddrhys;
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u32 grp_ddrmode;
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u32 grp_b0ds;
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u32 grp_b1ds;
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u32 grp_ctlds;
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u32 grp_ddr_type;
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u32 grp_b2ds;
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u32 grp_b3ds;
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};
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/*
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* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
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*/
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#define MX6DQ_IOM_DDR_BASE 0x020e0500
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struct mx6dq_iomux_ddr_regs {
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u32 res1[3];
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u32 dram_sdqs5;
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u32 dram_dqm5;
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u32 dram_dqm4;
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u32 dram_sdqs4;
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u32 dram_sdqs3;
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u32 dram_dqm3;
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u32 dram_sdqs2;
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u32 dram_dqm2;
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u32 res2[16];
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u32 dram_cas;
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u32 res3[2];
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u32 dram_ras;
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u32 dram_reset;
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u32 res4[2];
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u32 dram_sdclk_0;
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u32 dram_sdba2;
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u32 dram_sdcke0;
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u32 dram_sdclk_1;
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u32 dram_sdcke1;
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u32 dram_sdodt0;
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u32 dram_sdodt1;
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u32 res5;
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u32 dram_sdqs0;
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u32 dram_dqm0;
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u32 dram_sdqs1;
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u32 dram_dqm1;
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u32 dram_sdqs6;
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u32 dram_dqm6;
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u32 dram_sdqs7;
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u32 dram_dqm7;
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};
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#define MX6DQ_IOM_GRP_BASE 0x020e0700
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struct mx6dq_iomux_grp_regs {
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u32 res1[18];
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u32 grp_b7ds;
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u32 grp_addds;
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u32 grp_ddrmode_ctl;
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u32 res2;
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u32 grp_ddrpke;
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u32 res3[6];
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u32 grp_ddrmode;
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u32 res4[3];
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u32 grp_b0ds;
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u32 grp_b1ds;
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u32 grp_ctlds;
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u32 res5;
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u32 grp_b2ds;
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u32 grp_ddr_type;
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u32 grp_b3ds;
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u32 grp_b4ds;
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u32 grp_b5ds;
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u32 grp_b6ds;
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};
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#define MX6SDL_IOM_DDR_BASE 0x020e0400
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struct mx6sdl_iomux_ddr_regs {
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u32 res1[25];
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u32 dram_cas;
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u32 res2[2];
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u32 dram_dqm0;
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u32 dram_dqm1;
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u32 dram_dqm2;
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u32 dram_dqm3;
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u32 dram_dqm4;
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u32 dram_dqm5;
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u32 dram_dqm6;
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u32 dram_dqm7;
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u32 dram_ras;
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u32 dram_reset;
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u32 res3[2];
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u32 dram_sdba2;
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u32 dram_sdcke0;
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u32 dram_sdcke1;
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u32 dram_sdclk_0;
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u32 dram_sdclk_1;
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u32 dram_sdodt0;
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u32 dram_sdodt1;
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u32 dram_sdqs0;
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u32 dram_sdqs1;
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u32 dram_sdqs2;
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u32 dram_sdqs3;
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u32 dram_sdqs4;
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u32 dram_sdqs5;
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u32 dram_sdqs6;
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u32 dram_sdqs7;
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};
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#define MX6SDL_IOM_GRP_BASE 0x020e0700
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struct mx6sdl_iomux_grp_regs {
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u32 res1[18];
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u32 grp_b7ds;
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u32 grp_addds;
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u32 grp_ddrmode_ctl;
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u32 grp_ddrpke;
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u32 res2[2];
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u32 grp_ddrmode;
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u32 grp_b0ds;
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u32 res3;
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u32 grp_ctlds;
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u32 grp_b1ds;
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u32 grp_ddr_type;
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u32 grp_b2ds;
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u32 grp_b3ds;
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u32 grp_b4ds;
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u32 grp_b5ds;
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u32 res4;
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u32 grp_b6ds;
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};
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/* Device Information: Varies per DDR3 part number and speed grade */
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struct mx6_ddr3_cfg {
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u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
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u8 density; /* chip density (Gb) (1,2,4,8) */
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u8 width; /* bus width (bits) (4,8,16) */
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u8 banks; /* number of banks */
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u8 rowaddr; /* row address bits (11-16)*/
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u8 coladdr; /* col address bits (9-12) */
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u8 pagesz; /* page size (K) (1-2) */
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u16 trcd; /* tRCD=tRP=CL (ns*100) */
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u16 trcmin; /* tRC min (ns*100) */
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u16 trasmin; /* tRAS min (ns*100) */
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u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
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};
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/* System Information: Varies per board design, layout, and term choices */
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struct mx6_ddr_sysinfo {
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u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
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u8 cs_density; /* density per chip select (Gb) */
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u8 ncs; /* number chip selects used (1|2) */
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char cs1_mirror;/* enable address mirror (0|1) */
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char bi_on; /* Bank interleaving enable */
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u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
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u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
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u8 ralat; /* Read Additional Latency (0-7) */
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u8 walat; /* Write Additional Latency (0-3) */
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u8 mif3_mode; /* Command prediction working mode */
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u8 rst_to_cke; /* Time from SDE enable to CKE rise */
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u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
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u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
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};
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/*
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* Board specific calibration:
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* This includes write leveling calibration values as well as DQS gating
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* and read/write delays. These values are board/layout/device specific.
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* Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
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* (DOC-96412) to determine these values over a range of boards and
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* temperatures.
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*/
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struct mx6_mmdc_calibration {
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/* write leveling calibration */
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u32 p0_mpwldectrl0;
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u32 p0_mpwldectrl1;
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u32 p1_mpwldectrl0;
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u32 p1_mpwldectrl1;
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/* read DQS gating */
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u32 p0_mpdgctrl0;
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u32 p0_mpdgctrl1;
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u32 p1_mpdgctrl0;
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u32 p1_mpdgctrl1;
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/* read delay */
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u32 p0_mprddlctl;
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u32 p1_mprddlctl;
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/* write delay */
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u32 p0_mpwrdlctl;
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u32 p1_mpwrdlctl;
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};
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/* configure iomux (pinctl/padctl) */
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void mx6dq_dram_iocfg(unsigned width,
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const struct mx6dq_iomux_ddr_regs *,
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const struct mx6dq_iomux_grp_regs *);
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void mx6sdl_dram_iocfg(unsigned width,
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const struct mx6sdl_iomux_ddr_regs *,
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const struct mx6sdl_iomux_grp_regs *);
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void mx6sx_dram_iocfg(unsigned width,
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const struct mx6sx_iomux_ddr_regs *,
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const struct mx6sx_iomux_grp_regs *);
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/* configure mx6 mmdc registers */
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
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const struct mx6_mmdc_calibration *,
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const struct mx6_ddr3_cfg *);
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#endif /* CONFIG_SPL_BUILD */
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#define MX6_MMDC_P0_MDCTL 0x021b0000
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#define MX6_MMDC_P0_MDPDC 0x021b0004
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#define MX6_MMDC_P0_MDOTC 0x021b0008
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#define MX6_MMDC_P0_MDCFG0 0x021b000c
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#define MX6_MMDC_P0_MDCFG1 0x021b0010
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#define MX6_MMDC_P0_MDCFG2 0x021b0014
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#define MX6_MMDC_P0_MDMISC 0x021b0018
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#define MX6_MMDC_P0_MDSCR 0x021b001c
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#define MX6_MMDC_P0_MDREF 0x021b0020
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#define MX6_MMDC_P0_MDRWD 0x021b002c
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#define MX6_MMDC_P0_MDOR 0x021b0030
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#define MX6_MMDC_P0_MDASP 0x021b0040
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#define MX6_MMDC_P0_MAPSR 0x021b0404
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#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
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#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
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#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
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#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
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#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
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#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
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#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
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#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
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#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
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#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
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#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
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#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
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#define MX6_MMDC_P0_MPMUR0 0x021b08b8
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#define MX6_MMDC_P1_MDCTL 0x021b4000
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#define MX6_MMDC_P1_MDPDC 0x021b4004
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#define MX6_MMDC_P1_MDOTC 0x021b4008
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#define MX6_MMDC_P1_MDCFG0 0x021b400c
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#define MX6_MMDC_P1_MDCFG1 0x021b4010
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#define MX6_MMDC_P1_MDCFG2 0x021b4014
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#define MX6_MMDC_P1_MDMISC 0x021b4018
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#define MX6_MMDC_P1_MDSCR 0x021b401c
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#define MX6_MMDC_P1_MDREF 0x021b4020
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#define MX6_MMDC_P1_MDRWD 0x021b402c
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#define MX6_MMDC_P1_MDOR 0x021b4030
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#define MX6_MMDC_P1_MDASP 0x021b4040
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#define MX6_MMDC_P1_MAPSR 0x021b4404
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#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
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#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
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#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
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#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
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#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
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#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
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#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
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#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
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#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
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#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
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#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
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#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
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#define MX6_MMDC_P1_MPMUR0 0x021b48b8
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#endif /*__ASM_ARCH_MX6_DDR_H__ */
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