Shaveta Leekha b6808cd82d powerpc/serdes: Add the workaround for erratum A-007186 ... SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com>		2014-06-05 13:45:07 -07:00
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cpu	powerpc/serdes: Add the workaround for erratum A-007186	2014-06-05 13:45:07 -07:00
include/asm	powerpc/serdes: Add the workaround for erratum A-007186	2014-06-05 13:45:07 -07:00
lib	m68k: powerpc: Clean up do_mdm_init	2014-05-29 17:49:33 -04:00
config.mk	kbuild: move "checkgcc4" to PowerPC archprepare	2014-03-07 10:59:07 -05:00