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u-boot-brain/board/freescale/p1_p2_rdb_pc
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Simon Glass b63ff2ae54 common: Move clock functions into a new file 
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:48 +05:30
..
ddr.c Move strtomhz() to vsprintf.h 2019-12-02 18:23:09 -05:00
Kconfig powerpc: P1_P2_RDB_PC: Drop TARGET_P1_P2_RDB_PC 2016-11-23 23:42:09 -08:00
law.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
MAINTAINERS MAINTAINERS: comment out blank M: field 2014-09-24 18:30:28 -04:00
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
p1_p2_rdb_pc.c common: Move some board functions out of common.h 2019-12-02 18:25:21 -05:00
README powerpc: Enable device tree support for P2020RDB 2019-08-26 21:23:22 +05:30
spl_minimal.c common: Move relocate_code() to init.h 2020-01-24 23:06:48 +05:30
spl.c common: Move clock functions into a new file 2020-01-24 23:06:48 +05:30
tlb.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00

README 

Overview
--------
P1_P2_RDB_PC represents a set of boards including
    P1020MSBG-PC
    P1020RDB-PC
    P1020RDB-PD
    P1020UTM-PC
    P1021RDB-PC
    P1024RDB
    P1025RDB
    P2020RDB-PC

They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
has 64-bit DDR. All others have 32-bit DDR.

Key features on these boards include:
    * DDR3
    * NOR flash
    * NAND flash (on RDB's only)
    * SPI flash (on RDB's only)
    * SDHC/MMC card slot
    * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
    * PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported with
this approach. ODT option is forced to fit this set of boards, again because
they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
pins multiplexing. QE function needs to be disabled to access Nor Flash and
CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.

Device tree support and how to enable it for different configs
--------------------------------------------------------------
Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
1. NOR Boot
2. NAND Boot
3. SD Boot
4. SPIFLASH Boot

To enable device tree support for other boot, below configs need to be
enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
   CONFIG_RESET_VECTOR_ADDRESS - 0xffc

If device tree support is enabled in defconfig,
1. use 'u-boot-with-dtb.bin' for NOR boot.
2. use 'u-boot-with-spl.bin' for other boot.