mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 22:56:17 +09:00
e9ccb2f526
Add core architecture code to support the px30 soc. This includes a separate tpl board file due to very limited sram size as well as a non-dm sdram driver, as this also has to fit into the tiny sram. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
32 lines
579 B
C
32 lines
579 B
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <syscon.h>
|
|
#include <asm/arch-rockchip/clock.h>
|
|
#include <asm/arch-rockchip/cru_px30.h>
|
|
|
|
int rockchip_get_clk(struct udevice **devp)
|
|
{
|
|
return uclass_get_device_by_driver(UCLASS_CLK,
|
|
DM_GET_DRIVER(rockchip_px30_cru), devp);
|
|
}
|
|
|
|
void *rockchip_get_cru(void)
|
|
{
|
|
struct px30_clk_priv *priv;
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = rockchip_get_clk(&dev);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
priv = dev_get_priv(dev);
|
|
|
|
return priv->cru;
|
|
}
|