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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
c2a2123e33
If dcache is switched OFF to ON state and if non-cached memory is used, this non-cached memory must be re-declared as uncached to mmu each time dcache is set ON. Introduce noncached_set_region() to set this non-cached region's mmu settings. Let architecture override it by defining it as a weak function. For ARM architecture, noncached_set_region() defines all noncached region as non-cacheable. Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver, when going from dcache OFF to dcache ON state, ethernet driver issued TX timeout errors when performing dhcp or ping. It can be reproduced with the following sequence: dhcp while true ; do ping 192.168.1.300 ; dcache off ; ping 192.168.1.300 ; dcache on ; done Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de>
116 lines
2.2 KiB
C
116 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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/*
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* Cache support: switch on or off, get status
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <linux/compiler.h>
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static int parse_argv(const char *);
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void __weak invalidate_icache_all(void)
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{
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/* please define arch specific invalidate_icache_all */
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puts("No arch specific invalidate_icache_all available!\n");
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}
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__weak void noncached_set_region(void)
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{
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}
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static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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switch (argc) {
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case 2: /* on / off / flush */
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switch (parse_argv(argv[1])) {
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case 0:
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icache_disable();
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break;
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case 1:
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icache_enable();
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break;
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case 2:
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invalidate_icache_all();
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break;
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default:
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return CMD_RET_USAGE;
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}
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break;
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case 1: /* get status */
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printf("Instruction Cache is %s\n",
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icache_status() ? "ON" : "OFF");
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return 0;
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default:
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return CMD_RET_USAGE;
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}
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return 0;
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}
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void __weak flush_dcache_all(void)
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{
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puts("No arch specific flush_dcache_all available!\n");
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/* please define arch specific flush_dcache_all */
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}
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static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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switch (argc) {
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case 2: /* on / off / flush */
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switch (parse_argv(argv[1])) {
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case 0:
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dcache_disable();
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break;
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case 1:
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dcache_enable();
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noncached_set_region();
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break;
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case 2:
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flush_dcache_all();
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break;
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default:
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return CMD_RET_USAGE;
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}
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break;
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case 1: /* get status */
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printf("Data (writethrough) Cache is %s\n",
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dcache_status() ? "ON" : "OFF");
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return 0;
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default:
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return CMD_RET_USAGE;
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}
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return 0;
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}
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static int parse_argv(const char *s)
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{
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if (strcmp(s, "flush") == 0)
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return 2;
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else if (strcmp(s, "on") == 0)
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return 1;
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else if (strcmp(s, "off") == 0)
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return 0;
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return -1;
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}
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U_BOOT_CMD(
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icache, 2, 1, do_icache,
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"enable or disable instruction cache",
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"[on, off, flush]\n"
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" - enable, disable, or flush instruction cache"
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);
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U_BOOT_CMD(
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dcache, 2, 1, do_dcache,
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"enable or disable data cache",
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"[on, off, flush]\n"
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" - enable, disable, or flush data (writethrough) cache"
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);
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