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b615267633
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/*
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* (c) Copyright 2016, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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*
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* Based on jetson-tk1.h which is:
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* (C) Copyright 2013-2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/sizes.h>
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/* enable PMIC */
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#define CONFIG_AS3722_POWER
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#include "tegra124-common.h"
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/* High-level configuration options */
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#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som"
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/* Board-specific serial config */
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#define CONFIG_TEGRA_ENABLE_UARTD
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#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_TEGRA_MMC
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 2
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/* SPI */
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 24000000
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#define CONFIG_SPI_FLASH_SIZE (4 << 20)
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/* USB Host support */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_TEGRA
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#define CONFIG_USB_STORAGE
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/* USB networking support */
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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/* General networking support */
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#include "tegra-common-usb-gadget.h"
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#include "tegra-common-post.h"
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#define CONFIG_ARMV7_PSCI 1
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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/* Reserve top 1M for secure RAM */
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#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
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#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
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#endif /* __CONFIG_H */
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