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b615267633
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* (C) Copyright 2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <power/as3722.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-cei-tk1-som.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_clear_tristate_input_clamping();
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gpio_config_table(cei_tk1_som_gpio_inits,
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ARRAY_SIZE(cei_tk1_som_gpio_inits));
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pinmux_config_pingrp_table(cei_tk1_som_pingrps,
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ARRAY_SIZE(cei_tk1_som_pingrps));
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pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
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ARRAY_SIZE(cei_tk1_som_drvgrps));
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pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
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ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
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}
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#ifdef CONFIG_PCI_TEGRA
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int tegra_pcie_board_init(void)
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{
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struct udevice *pmic;
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int err;
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err = as3722_init(&pmic);
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if (err) {
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error("failed to initialize AS3722 PMIC: %d\n", err);
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return err;
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}
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err = as3722_sd_enable(pmic, 4);
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if (err < 0) {
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error("failed to enable SD4: %d\n", err);
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return err;
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}
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err = as3722_sd_set_voltage(pmic, 4, 0x24);
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if (err < 0) {
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error("failed to set SD4 voltage: %d\n", err);
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return err;
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}
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return 0;
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}
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#endif /* PCI */
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