mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Masahiro Yamada](/assets/img/avatar_default.png)
These are used by Panasonic UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sbc-regs.h>
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#include <asm/arch/sg-regs.h>
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void sbc_init(void)
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{
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#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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*/
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
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if (readl(SBBASE0) & 0x1) {
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/*
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* Boot Swap Off: boot from mask ROM
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* 0x00000000-0x01ffffff: mask ROM
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* 0x02000000-0x3effffff: memory bank (31MB)
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* 0x03f00000-0x3fffffff: peripherals (1MB)
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*/
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writel(0x0000be01, SBBASE0); /* dummy */
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writel(0x0200be01, SBBASE1);
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} else {
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/*
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* Boot Swap On: boot from external NOR/SRAM
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* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
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*
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* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
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* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
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*/
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writel(0x0000bc01, SBBASE0);
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}
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#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
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#if !defined(CONFIG_SPL_BUILD)
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/* XECS0: boot/sub memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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#endif
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/* XECS1: sub/boot memory (boot swap = off/on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/* XECS3: peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0400bc01, SBBASE1); /* sub memory */
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writel(0x0800bf01, SBBASE3); /* peripherals */
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#if !defined(CONFIG_SPL_BUILD)
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sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
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#endif
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sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
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writel(0x00000001, SG_LOADPINCTRL);
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#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
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}
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