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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
Previously, 85xx and 86xx boards would display DRAM information on bootup such as: ... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ... This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner: ... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
206 lines
4.6 KiB
C
206 lines
4.6 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include "ddr.h"
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unsigned int fsl_ddr_get_mem_data_rate(void);
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/*
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* Round mclk_ps to nearest 10 ps in memory controller code.
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*
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* If an imprecise data rate is too high due to rounding error
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* propagation, compute a suitably rounded mclk_ps to compute
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* a working memory controller configuration.
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*/
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unsigned int get_memory_clk_period_ps(void)
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{
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unsigned int mclk_ps;
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mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
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/* round to nearest 10 ps */
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return 10 * ((mclk_ps + 5) / 10);
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}
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/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
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unsigned int picos_to_mclk(unsigned int picos)
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{
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const unsigned long long ULL_2e12 = 2000000000000ULL;
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const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
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unsigned long long clks;
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unsigned long long clks_temp;
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if (!picos)
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return 0;
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clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
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clks_temp = clks;
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clks = clks / ULL_2e12;
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if (clks_temp % ULL_2e12) {
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clks++;
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}
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if (clks > ULL_8Fs) {
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clks = ULL_8Fs;
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}
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return (unsigned int) clks;
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}
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unsigned int mclk_to_picos(unsigned int mclk)
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{
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return get_memory_clk_period_ps() * mclk;
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}
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void
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__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num)
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{
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unsigned long long base = memctl_common_params->base_address;
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unsigned long long size = memctl_common_params->total_mem;
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/*
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* If no DIMMs on this controller, do not proceed any further.
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*/
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if (!memctl_common_params->ndimms_present) {
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return;
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}
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#if !defined(CONFIG_PHYS_64BIT)
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if (base >= CONFIG_MAX_MEM_MAPPED)
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return;
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if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
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size = CONFIG_MAX_MEM_MAPPED - base;
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#endif
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if (ctrl_num == 0) {
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/*
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* Set up LAW for DDR controller 1 space.
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*/
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unsigned int lawbar1_target_id = memctl_interleaved
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? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else if (ctrl_num == 1) {
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if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else {
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printf("unexpected controller number %u in %s\n",
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ctrl_num, __FUNCTION__);
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}
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}
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__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
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fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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void board_add_ram_info(int use_default)
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{
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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#elif defined(CONFIG_MPC86xx)
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
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#endif
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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uint32_t cs0_config = in_be32(&ddr->cs0_config);
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#endif
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uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
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int cas_lat;
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puts(" (DDR");
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switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
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SDRAM_CFG_SDRAM_TYPE_SHIFT) {
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case SDRAM_TYPE_DDR1:
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puts("1");
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break;
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case SDRAM_TYPE_DDR2:
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puts("2");
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break;
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case SDRAM_TYPE_DDR3:
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puts("3");
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break;
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default:
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puts("?");
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break;
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}
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if (sdram_cfg & SDRAM_CFG_32_BE)
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puts(", 32-bit");
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else
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puts(", 64-bit");
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/* Calculate CAS latency based on timing cfg values */
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cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
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if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
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cas_lat += (8 << 1);
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printf(", CL=%d", cas_lat >> 1);
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if (cas_lat & 0x1)
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puts(".5");
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if (sdram_cfg & SDRAM_CFG_ECC_EN)
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puts(", ECC on)");
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else
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puts(", ECC off)");
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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if (cs0_config & 0x20000000) {
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puts("\n");
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puts(" DDR Controller Interleaving Mode: ");
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switch ((cs0_config >> 24) & 0xf) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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puts("cache line");
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break;
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case FSL_DDR_PAGE_INTERLEAVING:
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puts("page");
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break;
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case FSL_DDR_BANK_INTERLEAVING:
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puts("bank");
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break;
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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puts("super-bank");
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break;
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default:
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puts("invalid");
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break;
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}
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}
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#endif
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if ((sdram_cfg >> 8) & 0x7f) {
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puts("\n");
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puts(" DDR Chip-Select Interleaving Mode: ");
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switch(sdram_cfg >> 8 & 0x7f) {
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case FSL_DDR_CS0_CS1_CS2_CS3:
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puts("CS0+CS1+CS2+CS3");
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break;
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case FSL_DDR_CS0_CS1:
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puts("CS0+CS1");
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break;
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case FSL_DDR_CS2_CS3:
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puts("CS2+CS3");
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break;
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case FSL_DDR_CS0_CS1_AND_CS2_CS3:
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puts("CS0+CS1 and CS2+CS3");
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break;
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default:
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puts("invalid");
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break;
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}
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}
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}
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