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https://github.com/brain-hackers/u-boot-brain
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b5e01eecc8
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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| .. | ||
| arm_intcm | ||
| arm720t | ||
| arm920t | ||
| arm926ejs | ||
| arm946es | ||
| arm1136 | ||
| arm1176 | ||
| armv7 | ||
| at91-common | ||
| ixp | ||
| pxa | ||
| sa1100 | ||
| tegra-common | ||
| tegra20-common | ||
| tegra30-common | ||
| tegra114-common | ||
| Makefile | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||