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https://github.com/brain-hackers/u-boot-brain
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2b21cf55cc
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happens on SAMA5D2 as exitting from the ROM code. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_COMMON_H
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#define AT91_COMMON_H
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void at91_can_hw_init(void);
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void at91_gmac_hw_init(void);
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void at91_macb_hw_init(void);
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void at91_mci_hw_init(void);
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void at91_serial0_hw_init(void);
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void at91_serial1_hw_init(void);
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void at91_serial2_hw_init(void);
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void at91_seriald_hw_init(void);
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void at91_spi0_hw_init(unsigned long cs_mask);
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void at91_spi1_hw_init(unsigned long cs_mask);
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void at91_udp_hw_init(void);
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void at91_uhp_hw_init(void);
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void at91_lcd_hw_init(void);
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void at91_plla_init(u32 pllar);
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void at91_pllb_init(u32 pllar);
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void at91_mck_init(u32 mckr);
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void at91_mck_init_down(u32 mckr);
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void at91_pmc_init(void);
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void mem_init(void);
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void at91_phy_reset(void);
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void at91_sdram_hw_init(void);
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void at91_mck_init(u32 mckr);
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void at91_spl_board_init(void);
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void at91_disable_wdt(void);
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void matrix_init(void);
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void redirect_int_from_saic_to_aic(void);
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void configure_2nd_sram_as_l2_cache(void);
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int at91_set_ethaddr(int offset);
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int at91_video_show_board_info(void);
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#endif /* AT91_COMMON_H */
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