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https://github.com/brain-hackers/u-boot-brain
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This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* (C) Copyright 2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <power/as3722.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-jetson-tk1.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_clear_tristate_input_clamping();
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gpio_config_table(jetson_tk1_gpio_inits,
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ARRAY_SIZE(jetson_tk1_gpio_inits));
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pinmux_config_pingrp_table(jetson_tk1_pingrps,
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ARRAY_SIZE(jetson_tk1_pingrps));
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pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
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ARRAY_SIZE(jetson_tk1_drvgrps));
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pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
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ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
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}
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#ifdef CONFIG_PCI_TEGRA
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int tegra_pcie_board_init(void)
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{
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struct udevice *pmic;
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int err;
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err = as3722_init(&pmic);
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if (err) {
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error("failed to initialize AS3722 PMIC: %d\n", err);
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return err;
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}
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err = as3722_sd_enable(pmic, 4);
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if (err < 0) {
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error("failed to enable SD4: %d\n", err);
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return err;
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}
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err = as3722_sd_set_voltage(pmic, 4, 0x24);
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if (err < 0) {
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error("failed to set SD4 voltage: %d\n", err);
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return err;
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}
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return 0;
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}
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#endif /* PCI */
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