Ken Ma b5a6c94a03 pinctrl: a3700: Fix uart2 group selection register mask ... If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>		2017-06-23 07:09:40 +02:00
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Kconfig	pinctrl: mvebu: Enable support for the Armada 37xx pinctrl driver	2017-05-31 07:33:50 +02:00
Makefile	pinctrl: mvebu: Enable support for the Armada 37xx pinctrl driver	2017-05-31 07:33:50 +02:00
pinctrl-armada-37xx.c	pinctrl: a3700: Fix uart2 group selection register mask	2017-06-23 07:09:40 +02:00
pinctrl-mvebu.c	dm: Rename dev_addr..() functions	2017-06-01 07:03:01 -06:00
pinctrl-mvebu.h	arm64: mvebu: pinctrl: Add pin control driver for A8K family	2016-12-12 09:04:52 +01:00