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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
208 lines
4.9 KiB
C
208 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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struct cpsw_mdio_regs {
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u32 version;
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u32 control;
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#define CONTROL_IDLE BIT(31)
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#define CONTROL_ENABLE BIT(30)
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#define CONTROL_FAULT BIT(19)
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#define CONTROL_FAULT_ENABLE BIT(18)
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#define CONTROL_DIV_MASK GENMASK(15, 0)
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u32 alive;
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u32 link;
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u32 linkintraw;
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u32 linkintmasked;
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u32 __reserved_0[2];
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u32 userintraw;
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u32 userintmasked;
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u32 userintmaskset;
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u32 userintmaskclr;
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u32 __reserved_1[20];
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struct {
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u32 access;
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u32 physel;
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#define USERACCESS_GO BIT(31)
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#define USERACCESS_WRITE BIT(30)
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#define USERACCESS_ACK BIT(29)
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#define USERACCESS_READ (0)
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#define USERACCESS_PHY_REG_SHIFT (21)
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#define USERACCESS_PHY_ADDR_SHIFT (16)
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#define USERACCESS_DATA GENMASK(15, 0)
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} user[0];
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};
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#define CPSW_MDIO_DIV_DEF 0xff
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#define PHY_REG_MASK 0x1f
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#define PHY_ID_MASK 0x1f
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/*
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* This timeout definition is a worst-case ultra defensive measure against
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* unexpected controller lock ups. Ideally, we should never ever hit this
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* scenario in practice.
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*/
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#define CPSW_MDIO_TIMEOUT 100 /* msecs */
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struct cpsw_mdio {
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struct cpsw_mdio_regs *regs;
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struct mii_dev *bus;
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int div;
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};
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/* wait until hardware is ready for another user access */
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static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
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{
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return wait_for_bit_le32(&mdio->regs->user[0].access,
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USERACCESS_GO, false,
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CPSW_MDIO_TIMEOUT, false);
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}
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static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
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int dev_addr, int phy_reg)
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{
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struct cpsw_mdio *mdio = bus->priv;
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int data, ret;
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u32 reg;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = (USERACCESS_GO | USERACCESS_READ |
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(phy_reg << USERACCESS_PHY_REG_SHIFT) |
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(phy_id << USERACCESS_PHY_ADDR_SHIFT));
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writel(reg, &mdio->regs->user[0].access);
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = readl(&mdio->regs->user[0].access);
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data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
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return data;
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}
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static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
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int phy_reg, u16 data)
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{
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struct cpsw_mdio *mdio = bus->priv;
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u32 reg;
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int ret;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = (USERACCESS_GO | USERACCESS_WRITE |
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(phy_reg << USERACCESS_PHY_REG_SHIFT) |
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(phy_id << USERACCESS_PHY_ADDR_SHIFT) |
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(data & USERACCESS_DATA));
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writel(reg, &mdio->regs->user[0].access);
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return cpsw_mdio_wait_for_user_access(mdio);
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}
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u32 cpsw_mdio_get_alive(struct mii_dev *bus)
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{
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struct cpsw_mdio *mdio = bus->priv;
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u32 val;
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val = readl(&mdio->regs->control);
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return val & GENMASK(15, 0);
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}
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struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
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u32 bus_freq, int fck_freq)
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{
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struct cpsw_mdio *cpsw_mdio;
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int ret;
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cpsw_mdio = calloc(1, sizeof(*cpsw_mdio));
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if (!cpsw_mdio) {
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debug("failed to alloc cpsw_mdio\n");
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return NULL;
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}
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cpsw_mdio->bus = mdio_alloc();
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if (!cpsw_mdio->bus) {
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debug("failed to alloc mii bus\n");
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free(cpsw_mdio);
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return NULL;
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}
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cpsw_mdio->regs = (struct cpsw_mdio_regs *)(uintptr_t)mdio_base;
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if (!bus_freq || !fck_freq)
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cpsw_mdio->div = CPSW_MDIO_DIV_DEF;
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else
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cpsw_mdio->div = (fck_freq / bus_freq) - 1;
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cpsw_mdio->div &= CONTROL_DIV_MASK;
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/* set enable and clock divider */
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writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT |
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CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control);
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wait_for_bit_le32(&cpsw_mdio->regs->control,
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CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
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/*
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* wait for scan logic to settle:
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* the scan time consists of (a) a large fixed component, and (b) a
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* small component that varies with the mii bus frequency. These
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* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
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* silicon. Since the effect of (b) was found to be largely
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* negligible, we keep things simple here.
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*/
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mdelay(1);
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cpsw_mdio->bus->read = cpsw_mdio_read;
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cpsw_mdio->bus->write = cpsw_mdio_write;
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cpsw_mdio->bus->priv = cpsw_mdio;
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snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
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ret = mdio_register(cpsw_mdio->bus);
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if (ret < 0) {
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debug("failed to register mii bus\n");
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goto free_bus;
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}
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return cpsw_mdio->bus;
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free_bus:
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mdio_free(cpsw_mdio->bus);
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free(cpsw_mdio);
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return NULL;
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}
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void cpsw_mdio_free(struct mii_dev *bus)
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{
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struct cpsw_mdio *mdio = bus->priv;
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u32 reg;
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/* disable mdio */
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reg = readl(&mdio->regs->control);
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reg &= ~CONTROL_ENABLE;
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writel(reg, &mdio->regs->control);
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mdio_unregister(bus);
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mdio_free(bus);
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free(mdio);
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}
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