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![Heiko Schocher](/assets/img/avatar_default.png)
add DM/DTS support for the UEC ethernet on QUICC Engine Block. Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com> Series-changes: 3 - revert: commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled") as now qe works with DM and DM_ETH support. - fix mailaddress from Holger Series-changes: 2 - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag Commit-notes: - I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS. - add the DM based qe uec driver under drivers/net/qe - Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes. - The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c - seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c END
164 lines
4.0 KiB
C
164 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* QE UEC ethernet phy controller driver
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*
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* based on phy parts of drivers/qe/uec.c and drivers/qe/uec_phy.c
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* from NXP
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <linux/ioport.h>
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#include "dm_qe_uec.h"
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struct qe_uec_mdio_priv {
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struct ucc_mii_mng *base;
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};
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static int
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qe_uec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
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struct ucc_mii_mng *regs = priv->base;
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u32 tmp_reg;
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u16 value;
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debug("%s: regs: %p addr: %x devad: %x reg: %x\n", __func__, regs,
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addr, devad, reg);
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/* Setting up the MII management Address Register */
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tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
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out_be32(®s->miimadd, tmp_reg);
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/* clear MII management command cycle */
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out_be32(®s->miimcom, 0);
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sync();
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/* Perform an MII management read cycle */
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out_be32(®s->miimcom, MIIMCOM_READ_CYCLE);
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/* Wait till MII management write is complete */
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while ((in_be32(®s->miimind)) &
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(MIIMIND_NOT_VALID | MIIMIND_BUSY))
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;
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/* Read MII management status */
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value = (u16)in_be32(®s->miimstat);
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if (value == 0xffff)
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return -EINVAL;
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return value;
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};
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static int
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qe_uec_mdio_write(struct udevice *dev, int addr, int devad, int reg,
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u16 value)
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{
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struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
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struct ucc_mii_mng *regs = priv->base;
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u32 tmp_reg;
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debug("%s: regs: %p addr: %x devad: %x reg: %x val: %x\n", __func__,
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regs, addr, devad, reg, value);
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/* Stop the MII management read cycle */
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out_be32(®s->miimcom, 0);
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/* Setting up the MII management Address Register */
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tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
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out_be32(®s->miimadd, tmp_reg);
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/* Setting up the MII management Control Register with the value */
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out_be32(®s->miimcon, (u32)value);
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sync();
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/* Wait till MII management write is complete */
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while ((in_be32(®s->miimind)) & MIIMIND_BUSY)
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;
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return 0;
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};
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static const struct mdio_ops qe_uec_mdio_ops = {
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.read = qe_uec_mdio_read,
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.write = qe_uec_mdio_write,
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};
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static int qe_uec_mdio_probe(struct udevice *dev)
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{
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struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
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fdt_size_t base;
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ofnode node;
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u32 num = 0;
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int ret = -ENODEV;
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priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
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base = (fdt_size_t)priv->base;
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/*
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* idea from linux:
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* drivers/net/ethernet/freescale/fsl_pq_mdio.c
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*
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* Find the UCC node that controls the given MDIO node
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*
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* For some reason, the QE MDIO nodes are not children of the UCC
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* devices that control them. Therefore, we need to scan all UCC
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* nodes looking for the one that encompases the given MDIO node.
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* We do this by comparing physical addresses. The 'start' and
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* 'end' addresses of the MDIO node are passed, and the correct
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* UCC node will cover the entire address range.
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*/
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node = ofnode_by_compatible(ofnode_null(), "ucc_geth");
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while (ofnode_valid(node)) {
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fdt_size_t size;
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fdt_addr_t addr;
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addr = ofnode_get_addr_index(node, 0);
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ret = ofnode_get_addr_size_index(node, 0, &size);
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if (addr == FDT_ADDR_T_NONE) {
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node = ofnode_by_compatible(node, "ucc_geth");
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continue;
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}
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/* check if priv->base in start end */
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if (base > addr && base < (addr + size)) {
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ret = ofnode_read_u32(node, "cell-index", &num);
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if (ret)
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ret = ofnode_read_u32(node, "device-id",
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&num);
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break;
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}
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node = ofnode_by_compatible(node, "ucc_geth");
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}
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if (ret) {
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printf("%s: no cell-index nor device-id found!", __func__);
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return ret;
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}
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/* Setup MII master clock source */
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qe_set_mii_clk_src(num - 1);
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return 0;
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}
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static const struct udevice_id qe_uec_mdio_ids[] = {
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{ .compatible = "fsl,ucc-mdio" },
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{ }
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};
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U_BOOT_DRIVER(mvmdio) = {
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.name = "qe_uec_mdio",
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.id = UCLASS_MDIO,
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.of_match = qe_uec_mdio_ids,
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.probe = qe_uec_mdio_probe,
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.ops = &qe_uec_mdio_ops,
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.priv_auto_alloc_size = sizeof(struct qe_uec_mdio_priv),
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};
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