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https://github.com/brain-hackers/u-boot-brain
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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
136 lines
2.9 KiB
ArmAsm
136 lines
2.9 KiB
ArmAsm
/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <mpc8xx.h>
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#include <ppc_asm.tmpl>
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#include <asm/cache.h>
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#define CACHE_CMD_ENABLE 0x02000000
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#define CACHE_CMD_DISABLE 0x04000000
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#define CACHE_CMD_LOAD_LOCK 0x06000000
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#define CACHE_CMD_UNLOCK_LINE 0x08000000
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#define CACHE_CMD_UNLOCK_ALL 0x0A000000
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#define CACHE_CMD_INVALIDATE 0x0C000000
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#define SPEED_PLPRCR_WAIT_5CYC 150
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#define _CACHE_ALIGN_SIZE 16
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.text
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.align 2
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.globl plprcr_write_866
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/*
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* void plprcr_write_866 (long plprcr)
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* Write PLPRCR, including workaround for device errata SIU4 and SIU9.
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*/
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plprcr_write_866:
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mfspr r10, LR /* save the Link Register value */
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/* turn instruction cache on (no MMU required for instructions)
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*/
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lis r4, CACHE_CMD_ENABLE@h
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ori r4, r4, CACHE_CMD_ENABLE@l
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mtspr IC_CST, r4
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isync
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/* clear IC_CST error bits
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*/
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mfspr r4, IC_CST
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bl plprcr_here
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plprcr_here:
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mflr r5
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/* calculate relocation offset
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*/
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lis r4, plprcr_here@h
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ori r4, r4, plprcr_here@l
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sub r5, r5, r4
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/* calculate first address of this function
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*/
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lis r6, plprcr_write_866@h
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ori r6, r6, plprcr_write_866@l
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add r6, r6, r5
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/* calculate end address of this function
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*/
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lis r7, plprcr_end@h
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ori r7, r7, plprcr_end@l
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add r7, r7, r5
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/* load and lock code addresses
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*/
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mr r5, r6
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plprcr_loop:
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mtspr IC_ADR, r5
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addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */
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lis r4, CACHE_CMD_LOAD_LOCK@h
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ori r4, r4, CACHE_CMD_LOAD_LOCK@l
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mtspr IC_CST, r4
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isync
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cmpw r5, r7
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blt plprcr_loop
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/* IC_CST error bits not evaluated
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*/
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/* switch PLPRCR
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*/
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mfspr r4, IMMR /* read IMMR */
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rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
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/* write sequence according to MPC866 Errata
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*/
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stw r3, PLPRCR(r4)
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isync
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lis r3, SPEED_PLPRCR_WAIT_5CYC@h
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ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l
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plprcr_wait:
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cmpwi r3, 0
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beq plprcr_wait_end
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nop
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subi r3, r3, 1
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b plprcr_wait
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plprcr_wait_end:
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/* unlock instruction cache but leave it enabled
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*/
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lis r4, CACHE_CMD_UNLOCK_ALL@h
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ori r4, r4, CACHE_CMD_UNLOCK_ALL@l
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mtspr IC_CST, r4
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isync
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mtspr LR, r10 /* restore original Link Register value */
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blr
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plprcr_end:
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