mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
61290fb52c
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_MHZ 375
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#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN 0x40000
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#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_LOAD_ADDR 0x81000000
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#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_CLK 25000000
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{9600, 19200, 38400, 57600, 115200}
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#define CONFIG_BOOTCOMMAND "sf probe;" \
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"mtdparts default;" \
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"bootm 0x9f060000"
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#define CONFIG_ENV_SPI_MAX_HZ 25000000
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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/* Miscellaneous configurable options */
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/*
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* Diagnostics
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*/
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#define CONFIG_SYS_MEMTEST_END 0x83f00000
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#endif /* __CONFIG_H */
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