Dave Gerlach b56b9a0884 ARM: AM43xx: Change DDR3 Reset Value ... The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>		2014-03-04 09:42:07 -05:00
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cpu	ARM: AM43xx: Change DDR3 Reset Value	2014-03-04 09:42:07 -05:00
dts	venice2: move device tree to fix build error	2014-02-20 12:00:20 -05:00
imx-common	kbuild: use shorten logs for IMX images	2014-02-25 11:01:29 -05:00
include/asm	Merge branch 'master' of git://git.denx.de/u-boot-arm	2014-02-26 16:49:58 -05:00
lib	Merge branch 'master' of git://git.denx.de/u-boot-arm	2014-02-26 16:49:58 -05:00
config.mk	kbuild: refactor more IMX image rules	2014-02-25 11:01:29 -05:00