mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 18:39:43 +09:00
b539534d12
We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
272 lines
6.4 KiB
C
272 lines
6.4 KiB
C
/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc.
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*
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* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
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* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
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* cpu specific common code for 85xx/86xx processors.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <tsec.h>
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#include <fm_eth.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct cpu_type cpu_type_list[] = {
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#if defined(CONFIG_MPC85xx)
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CPU_TYPE_ENTRY(8533, 8533, 1),
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CPU_TYPE_ENTRY(8535, 8535, 1),
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CPU_TYPE_ENTRY(8536, 8536, 1),
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CPU_TYPE_ENTRY(8540, 8540, 1),
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CPU_TYPE_ENTRY(8541, 8541, 1),
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CPU_TYPE_ENTRY(8543, 8543, 1),
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CPU_TYPE_ENTRY(8544, 8544, 1),
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CPU_TYPE_ENTRY(8545, 8545, 1),
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CPU_TYPE_ENTRY(8547, 8547, 1),
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CPU_TYPE_ENTRY(8548, 8548, 1),
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CPU_TYPE_ENTRY(8555, 8555, 1),
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CPU_TYPE_ENTRY(8560, 8560, 1),
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CPU_TYPE_ENTRY(8567, 8567, 1),
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CPU_TYPE_ENTRY(8568, 8568, 1),
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CPU_TYPE_ENTRY(8569, 8569, 1),
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CPU_TYPE_ENTRY(8572, 8572, 2),
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CPU_TYPE_ENTRY(P1010, P1010, 1),
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CPU_TYPE_ENTRY(P1011, P1011, 1),
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CPU_TYPE_ENTRY(P1012, P1012, 1),
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CPU_TYPE_ENTRY(P1013, P1013, 1),
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CPU_TYPE_ENTRY(P1014, P1014, 1),
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CPU_TYPE_ENTRY(P1017, P1017, 1),
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CPU_TYPE_ENTRY(P1020, P1020, 2),
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CPU_TYPE_ENTRY(P1021, P1021, 2),
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CPU_TYPE_ENTRY(P1022, P1022, 2),
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CPU_TYPE_ENTRY(P1023, P1023, 2),
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CPU_TYPE_ENTRY(P1024, P1024, 2),
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CPU_TYPE_ENTRY(P1025, P1025, 2),
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CPU_TYPE_ENTRY(P2010, P2010, 1),
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CPU_TYPE_ENTRY(P2020, P2020, 2),
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CPU_TYPE_ENTRY(P2040, P2040, 4),
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CPU_TYPE_ENTRY(P2041, P2041, 4),
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CPU_TYPE_ENTRY(P3041, P3041, 4),
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CPU_TYPE_ENTRY(P4040, P4040, 4),
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CPU_TYPE_ENTRY(P4080, P4080, 8),
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CPU_TYPE_ENTRY(P5010, P5010, 1),
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CPU_TYPE_ENTRY(P5020, P5020, 2),
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CPU_TYPE_ENTRY(P5021, P5021, 2),
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CPU_TYPE_ENTRY(P5040, P5040, 4),
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CPU_TYPE_ENTRY(T4240, T4240, 0),
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CPU_TYPE_ENTRY(T4120, T4120, 0),
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CPU_TYPE_ENTRY(T4160, T4160, 0),
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CPU_TYPE_ENTRY(T4080, T4080, 4),
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CPU_TYPE_ENTRY(B4860, B4860, 0),
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CPU_TYPE_ENTRY(G4860, G4860, 0),
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CPU_TYPE_ENTRY(G4060, G4060, 0),
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CPU_TYPE_ENTRY(B4440, B4440, 0),
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CPU_TYPE_ENTRY(G4440, G4440, 0),
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CPU_TYPE_ENTRY(B4420, B4420, 0),
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CPU_TYPE_ENTRY(B4220, B4220, 0),
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CPU_TYPE_ENTRY(T1040, T1040, 0),
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CPU_TYPE_ENTRY(T1041, T1041, 0),
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CPU_TYPE_ENTRY(T1042, T1042, 0),
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CPU_TYPE_ENTRY(T1020, T1020, 0),
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CPU_TYPE_ENTRY(T1021, T1021, 0),
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CPU_TYPE_ENTRY(T1022, T1022, 0),
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CPU_TYPE_ENTRY(T2080, T2080, 0),
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CPU_TYPE_ENTRY(T2081, T2081, 0),
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CPU_TYPE_ENTRY(BSC9130, 9130, 1),
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CPU_TYPE_ENTRY(BSC9131, 9131, 1),
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CPU_TYPE_ENTRY(BSC9132, 9132, 2),
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CPU_TYPE_ENTRY(BSC9232, 9232, 2),
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CPU_TYPE_ENTRY(C291, C291, 1),
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CPU_TYPE_ENTRY(C292, C292, 1),
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CPU_TYPE_ENTRY(C293, C293, 1),
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#elif defined(CONFIG_MPC86xx)
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CPU_TYPE_ENTRY(8610, 8610, 1),
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CPU_TYPE_ENTRY(8641, 8641, 2),
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CPU_TYPE_ENTRY(8641D, 8641D, 2),
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#endif
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};
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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static inline u32 init_type(u32 cluster, int init_id)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
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u32 type = in_be32(&gur->tp_ityp[idx]);
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if (type & TP_ITYP_AV)
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return type;
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return 0;
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}
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u32 compute_ppc_cpumask(void)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type, mask = 0;
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do {
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int j;
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cluster = in_be32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = init_type(cluster, j);
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if (type) {
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if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
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mask |= 1 << count;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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return mask;
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}
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int fsl_qoriq_core_to_cluster(unsigned int core)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster;
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do {
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int j;
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cluster = in_be32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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if (init_type(cluster, j)) {
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if (count == core)
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return i;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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return -1; /* cannot identify the cluster */
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}
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#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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/*
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* Before chassis genenration 2, the cpumask should be hard-coded.
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* In case of cpu type unknown or cpumask unset, use 1 as fail save.
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*/
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#define compute_ppc_cpumask() 1
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#define fsl_qoriq_core_to_cluster(x) x
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
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struct cpu_type *identify_cpu(u32 ver)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
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if (cpu_type_list[i].soc_ver == ver)
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return &cpu_type_list[i];
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}
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return &cpu_type_unknown;
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}
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#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
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#define MPC8xxx_PICFRR_NCPU_SHIFT 8
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/*
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* Return a 32-bit mask indicating which cores are present on this SOC.
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*/
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__weak u32 cpu_mask(void)
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{
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ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
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struct cpu_type *cpu = gd->arch.cpu;
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/* better to query feature reporting register than just assume 1 */
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if (cpu == &cpu_type_unknown)
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return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
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MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
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if (cpu->num_cores == 0)
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return compute_ppc_cpumask();
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return cpu->mask;
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}
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/*
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* Return the number of cores on this SOC.
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*/
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__weak int cpu_numcores(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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/*
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* Report # of cores in terms of the cpu_mask if we haven't
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* figured out how many there are yet
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*/
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if (cpu->num_cores == 0)
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return hweight32(cpu_mask());
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return cpu->num_cores;
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}
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/*
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* Check if the given core ID is valid
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*
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* Returns zero if it isn't, 1 if it is.
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*/
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int is_core_valid(unsigned int core)
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{
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return !!((1 << core) & cpu_mask());
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}
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int probecpu (void)
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{
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uint svr;
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uint ver;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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gd->arch.cpu = identify_cpu(ver);
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return 0;
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}
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/* Once in memory, compute mask & # cores once and save them off */
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int fixup_cpu(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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if (cpu->num_cores == 0) {
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cpu->mask = cpu_mask();
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cpu->num_cores = cpu_numcores();
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}
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return 0;
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_ETHER_ON_FCC)
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fec_initialize(bis);
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#endif
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#if defined(CONFIG_UEC_ETH)
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uec_standard_init(bis);
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
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tsec_standard_init(bis);
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#endif
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#ifdef CONFIG_FMAN_ENET
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fm_standard_init(bis);
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#endif
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return 0;
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}
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