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https://github.com/brain-hackers/u-boot-brain
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bf494d7e9b
Add SCFW macro definition. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef SC_PM_API_H
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#define SC_PM_API_H
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/* Defines for sc_pm_power_mode_t */
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#define SC_PM_PW_MODE_OFF 0U /* Power off */
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#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
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#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
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#define SC_PM_PW_MODE_ON 3U /* Power on */
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/* Defines for sc_pm_clk_t */
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#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
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#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
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#define SC_PM_CLK_PER 2U /* Peripheral clock */
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#define SC_PM_CLK_PHY 3U /* Phy clock */
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#define SC_PM_CLK_MISC 4U /* Misc clock */
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#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
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#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
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#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
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#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
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#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
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#define SC_PM_CLK_CPU 2U /* CPU clock */
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#define SC_PM_CLK_PLL 4U /* PLL */
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#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
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/* Defines for sc_pm_clk_mode_t */
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#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
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#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
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#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
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#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
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#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
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#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
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typedef u8 sc_pm_power_mode_t;
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typedef u8 sc_pm_clk_t;
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typedef u8 sc_pm_clk_mode_t;
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typedef u8 sc_pm_clk_parent_t;
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typedef u32 sc_pm_clock_rate_t;
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#endif /* SC_PM_API_H */
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