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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
297 lines
6.9 KiB
C
297 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#include <net.h>
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#include <net/pfe_eth/pfe_eth.h>
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#include <net/pfe_eth/pfe_mdio.h>
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struct gemac_s gem_info[] = {
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/* PORT_0 configuration */
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{
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/* GEMAC config */
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.gemac_speed = PFE_MAC_SPEED_1000M,
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.gemac_duplex = DUPLEX_FULL,
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/* phy iface */
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.phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
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.phy_mode = PHY_INTERFACE_MODE_SGMII,
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},
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/* PORT_1 configuration */
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{
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/* GEMAC config */
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.gemac_speed = PFE_MAC_SPEED_1000M,
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.gemac_duplex = DUPLEX_FULL,
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/* phy iface */
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.phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
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.phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
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},
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};
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static inline void pfe_gemac_enable(void *gemac_base)
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{
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writel(readl(gemac_base + EMAC_ECNTRL_REG) |
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EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
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}
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static inline void pfe_gemac_disable(void *gemac_base)
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{
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writel(readl(gemac_base + EMAC_ECNTRL_REG) &
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~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
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}
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static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
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u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
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u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
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~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
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if (speed == _1000BASET) {
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ecr |= EMAC_ECNTRL_SPEED;
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rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
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} else if (speed != _100BASET) {
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rcr |= EMAC_RCNTRL_RMII_10T;
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rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
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}
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writel(ecr, gemac_base + EMAC_ECNTRL_REG);
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out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
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/* remove loop back */
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rcr &= ~EMAC_RCNTRL_LOOP;
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/* enable flow control */
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rcr |= EMAC_RCNTRL_FCE;
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/* Enable MII mode */
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rcr |= EMAC_RCNTRL_MII_MODE;
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writel(rcr, gemac_base + EMAC_RCNTRL_REG);
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/* Enable Tx full duplex */
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writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
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gemac_base + EMAC_TCNTRL_REG);
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}
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static int pfe_eth_write_hwaddr(struct udevice *dev)
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{
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct gemac_s *gem = priv->gem;
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struct eth_pdata *pdata = dev_get_platdata(dev);
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uchar *mac = pdata->enetaddr;
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writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
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gem->gemac_base + EMAC_PHY_ADDR_LOW);
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writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
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EMAC_PHY_ADDR_HIGH);
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return 0;
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}
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/** Stops or Disables GEMAC pointing to this eth iface.
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*
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* @param[in] edev Pointer to eth device structure.
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*
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* @return none
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*/
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static inline void pfe_eth_stop(struct udevice *dev)
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{
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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pfe_gemac_disable(priv->gem->gemac_base);
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gpi_disable(priv->gem->egpi_base);
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}
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static int pfe_eth_start(struct udevice *dev)
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{
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct gemac_s *gem = priv->gem;
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int speed;
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/* set ethernet mac address */
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pfe_eth_write_hwaddr(dev);
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writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
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writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
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writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
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writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
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+ EMAC_TX_SECTION_EMPTY);
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writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
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+ EMAC_MIB_CTRL_STS_REG);
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#ifdef CONFIG_PHYLIB
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/* Start up the PHY */
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if (phy_startup(priv->phydev)) {
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printf("Could not initialize PHY %s\n",
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priv->phydev->dev->name);
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return -1;
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}
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speed = priv->phydev->speed;
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printf("Speed detected %x\n", speed);
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if (priv->phydev->duplex == DUPLEX_HALF) {
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printf("Half duplex not supported\n");
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return -1;
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}
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#endif
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pfe_gemac_set_speed(gem->gemac_base, speed);
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/* Enable GPI */
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gpi_enable(gem->egpi_base);
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/* Enable GEMAC */
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pfe_gemac_enable(gem->gemac_base);
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return 0;
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}
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static int pfe_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
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int rc;
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int i = 0;
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rc = pfe_send(priv->gemac_port, packet, length);
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if (rc < 0) {
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printf("Tx Queue full\n");
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return rc;
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}
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while (1) {
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rc = pfe_tx_done();
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if (rc == 0)
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break;
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udelay(100);
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i++;
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if (i == 30000)
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printf("Tx timeout, send failed\n");
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break;
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}
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return 0;
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}
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static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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uchar *pkt_buf;
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int len;
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int phy_port;
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len = pfe_recv(&pkt_buf, &phy_port);
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if (len == 0)
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return -EAGAIN; /* no packet in rx */
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else if (len < 0)
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return -EAGAIN;
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debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
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phy_port, len);
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if (phy_port != priv->gemac_port) {
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printf("Rx pkt not on expected port\n");
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return -EAGAIN;
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}
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*packetp = pkt_buf;
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return len;
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}
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static int pfe_eth_probe(struct udevice *dev)
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{
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct pfe_ddr_address *pfe_addr;
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struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
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int ret = 0;
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static int init_done;
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if (!init_done) {
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pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
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(struct pfe_ddr_address));
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if (!pfe_addr)
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return -ENOMEM;
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pfe_addr->ddr_pfe_baseaddr =
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(void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
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pfe_addr->ddr_pfe_phys_baseaddr =
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(unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
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debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
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pfe_addr->ddr_pfe_baseaddr,
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(u32)pfe_addr->ddr_pfe_phys_baseaddr);
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ret = pfe_drv_init(pfe_addr);
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if (ret)
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return ret;
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init_pfe_scfg_dcfg_regs();
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init_done = 1;
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}
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priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
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priv->gem = &gem_info[priv->gemac_port];
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priv->dev = dev;
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switch (priv->gemac_port) {
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case EMAC_PORT_0:
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default:
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priv->gem->gemac_base = EMAC1_BASE_ADDR;
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priv->gem->egpi_base = EGPI1_BASE_ADDR;
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break;
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case EMAC_PORT_1:
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priv->gem->gemac_base = EMAC2_BASE_ADDR;
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priv->gem->egpi_base = EGPI2_BASE_ADDR;
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break;
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}
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ret = pfe_eth_board_init(dev);
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if (ret)
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return ret;
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#if defined(CONFIG_PHYLIB)
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ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
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gem_info[priv->gemac_port].phy_address);
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#endif
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return ret;
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}
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static int pfe_eth_bind(struct udevice *dev)
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{
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struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
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char name[20];
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sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
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return device_set_name(dev, name);
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}
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static const struct eth_ops pfe_eth_ops = {
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.start = pfe_eth_start,
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.send = pfe_eth_send,
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.recv = pfe_eth_recv,
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.free_pkt = pfe_eth_free_pkt,
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.stop = pfe_eth_stop,
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.write_hwaddr = pfe_eth_write_hwaddr,
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};
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U_BOOT_DRIVER(pfe_eth) = {
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.name = "pfe_eth",
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.id = UCLASS_ETH,
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.bind = pfe_eth_bind,
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.probe = pfe_eth_probe,
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.remove = pfe_eth_remove,
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.ops = &pfe_eth_ops,
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.priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
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.platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
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};
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