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![Horatiu Vultur](/assets/img/avatar_default.png)
Add network driver for Microsemi Ethernet switch. It is present on ServalT SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
623 lines
16 KiB
C
623 lines
16 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Microsemi Corporation
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <dm/of_addr.h>
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#include <fdt_support.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <miiphy.h>
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#include <net.h>
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#include <wait_bit.h>
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#include "mscc_xfer.h"
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#define GCB_MIIM_MII_STATUS 0x0
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#define GCB_MIIM_STAT_BUSY BIT(3)
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#define GCB_MIIM_MII_CMD 0x8
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#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
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#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
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#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
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#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
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#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
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#define GCB_MIIM_MII_CMD_VLD BIT(31)
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#define GCB_MIIM_DATA 0xC
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#define GCB_MIIM_DATA_ERROR (0x3 << 16)
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#define PHY_CFG 0x0
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#define PHY_CFG_ENA 0x3
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#define PHY_CFG_COMMON_RST BIT(2)
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#define PHY_CFG_RST (0x3 << 3)
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#define PHY_STAT 0x4
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#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
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#define ANA_AC_RAM_CTRL_RAM_INIT 0x14fdc
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#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x15474
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#define ANA_CL_PORT_VLAN_CFG(x) (0xa018 + 0xc8 * (x))
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#define ANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19)
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#define ANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17)
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#define ANA_L2_COMMON_FWD_CFG 0x18498
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#define ANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6)
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#define ASM_CFG_STAT_CFG 0xb08
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#define ASM_CFG_PORT(x) (0xb74 + 0x4 * (x))
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#define ASM_CFG_PORT_NO_PREAMBLE_ENA BIT(8)
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#define ASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1)
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#define ASM_RAM_CTRL_RAM_INIT 0xbfc
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#define DEV_DEV_CFG_DEV_RST_CTRL 0x0
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#define DEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20)
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#define DEV_MAC_CFG_MAC_ENA 0x24
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#define DEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
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#define DEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
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#define DEV_MAC_CFG_MAC_IFG 0x3c
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#define DEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8)
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#define DEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4)
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#define DEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x)
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#define DEV_PCS1G_CFG_PCS1G_CFG 0x48
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#define DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0)
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#define DEV_PCS1G_CFG_PCS1G_MODE 0x4c
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#define DEV_PCS1G_CFG_PCS1G_SD 0x50
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#define DEV_PCS1G_CFG_PCS1G_ANEG 0x54
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#define DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16)
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#define LRN_COMMON_ACCESS_CTRL 0x0
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#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
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#define LRN_COMMON_MAC_ACCESS_CFG0 0x4
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#define LRN_COMMON_MAC_ACCESS_CFG1 0x8
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#define LRN_COMMON_MAC_ACCESS_CFG2 0xc
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_ADDR(x) (x)
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_TYPE(x) ((x) << 12)
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_VLD BIT(15)
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_LOCKED BIT(16)
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_COPY BIT(23)
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#define LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_QU(x) ((x) << 24)
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#define QFWD_SYSTEM_SWITCH_PORT_MODE(x) (0x4400 + 0x4 * (x))
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#define QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA BIT(17)
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#define QS_XTR_GRP_CFG(x) (4 * (x))
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#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
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#define QSYS_SYSTEM_RESET_CFG 0x1048
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#define QSYS_CALCFG_CAL_AUTO 0x1134
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#define QSYS_CALCFG_CAL_CTRL 0x113c
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#define QSYS_CALCFG_CAL_CTRL_CAL_MODE(x) ((x) << 11)
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#define QSYS_RAM_CTRL_RAM_INIT 0x1140
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#define REW_RAM_CTRL_RAM_INIT 0xFFF4
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#define MAC_VID 0
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#define CPU_PORT 11
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#define IFH_LEN 7
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#define ETH_ALEN 6
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#define PGID_BROADCAST 50
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#define PGID_UNICAST 51
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static const char * const regs_names[] = {
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"port0", "port1",
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"ana_ac", "ana_cl", "ana_l2", "asm", "lrn", "qfwd", "qs", "qsys", "rew",
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};
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#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
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#define MAX_PORT 2
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enum servalt_ctrl_regs {
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ANA_AC = MAX_PORT,
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ANA_CL,
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ANA_L2,
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ASM,
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LRN,
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QFWD,
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QS,
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QSYS,
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REW,
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};
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#define SERVALT_MIIM_BUS_COUNT 2
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struct servalt_phy_port_t {
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size_t phy_addr;
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struct mii_dev *bus;
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};
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struct servalt_private {
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void __iomem *regs[REGS_NAMES_COUNT];
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struct mii_dev *bus[SERVALT_MIIM_BUS_COUNT];
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struct servalt_phy_port_t ports[MAX_PORT];
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};
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struct mscc_miim_dev {
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void __iomem *regs;
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phys_addr_t miim_base;
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unsigned long miim_size;
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struct mii_dev *bus;
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};
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static const unsigned long servalt_regs_qs[] = {
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[MSCC_QS_XTR_RD] = 0x8,
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[MSCC_QS_XTR_FLUSH] = 0x18,
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[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
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[MSCC_QS_INJ_WR] = 0x2c,
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[MSCC_QS_INJ_CTRL] = 0x34,
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};
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static struct mscc_miim_dev miim[SERVALT_MIIM_BUS_COUNT];
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static int miim_count = -1;
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static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
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{
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return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
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GCB_MIIM_STAT_BUSY, false, 250, false);
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}
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static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
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u32 val;
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int ret;
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ret = mscc_miim_wait_ready(miim);
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if (ret)
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goto out;
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writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
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GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
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miim->regs + GCB_MIIM_MII_CMD);
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ret = mscc_miim_wait_ready(miim);
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if (ret)
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goto out;
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val = readl(miim->regs + GCB_MIIM_DATA);
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if (val & GCB_MIIM_DATA_ERROR) {
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ret = -EIO;
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goto out;
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}
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ret = val & 0xFFFF;
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out:
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return ret;
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}
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static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
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int ret;
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ret = mscc_miim_wait_ready(miim);
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if (ret < 0)
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goto out;
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writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
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GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
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GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
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out:
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return ret;
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}
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static struct mii_dev *servalt_mdiobus_init(phys_addr_t miim_base,
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unsigned long miim_size)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus)
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return NULL;
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++miim_count;
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sprintf(bus->name, "miim-bus%d", miim_count);
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miim[miim_count].regs = ioremap(miim_base, miim_size);
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miim[miim_count].miim_base = miim_base;
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miim[miim_count].miim_size = miim_size;
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bus->priv = &miim[miim_count];
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bus->read = mscc_miim_read;
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bus->write = mscc_miim_write;
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if (mdio_register(bus))
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return NULL;
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miim[miim_count].bus = bus;
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return bus;
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}
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static void mscc_phy_reset(void)
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{
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writel(0, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
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writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
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| PHY_CFG_ENA, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
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if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + GCB_PHY_CFG) +
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PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
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true, 2000, false)) {
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pr_err("Timeout in phy reset\n");
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}
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}
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static void servalt_cpu_capture_setup(struct servalt_private *priv)
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{
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/* ASM: No preamble and IFH prefix on CPU injected frames */
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writel(ASM_CFG_PORT_NO_PREAMBLE_ENA |
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ASM_CFG_PORT_INJ_FORMAT_CFG(1),
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priv->regs[ASM] + ASM_CFG_PORT(CPU_PORT));
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/* Set Manual injection via DEVCPU_QS registers for CPU queue 0 */
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writel(0x5, priv->regs[QS] + QS_INJ_GRP_CFG(0));
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/* Set Manual extraction via DEVCPU_QS registers for CPU queue 0 */
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writel(0x7, priv->regs[QS] + QS_XTR_GRP_CFG(0));
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/* Enable CPU port for any frame transfer */
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setbits_le32(priv->regs[QFWD] + QFWD_SYSTEM_SWITCH_PORT_MODE(CPU_PORT),
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QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA);
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/* Send a copy to CPU when found as forwarding entry */
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setbits_le32(priv->regs[ANA_L2] + ANA_L2_COMMON_FWD_CFG,
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ANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA);
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}
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static void servalt_port_init(struct servalt_private *priv, int port)
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{
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void __iomem *regs = priv->regs[port];
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/* Enable PCS */
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writel(DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA,
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regs + DEV_PCS1G_CFG_PCS1G_CFG);
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/* Disable Signal Detect */
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writel(0, regs + DEV_PCS1G_CFG_PCS1G_SD);
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/* Enable MAC RX and TX */
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writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
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DEV_MAC_CFG_MAC_ENA_TX_ENA,
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regs + DEV_MAC_CFG_MAC_ENA);
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/* Clear sgmii_mode_ena */
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writel(0, regs + DEV_PCS1G_CFG_PCS1G_MODE);
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/*
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* Clear sw_resolve_ena(bit 0) and set adv_ability to
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* something meaningful just in case
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*/
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writel(DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(0x20),
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regs + DEV_PCS1G_CFG_PCS1G_ANEG);
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/* Set MAC IFG Gaps */
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writel(DEV_MAC_CFG_MAC_IFG_TX_IFG(4) |
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DEV_MAC_CFG_MAC_IFG_RX_IFG1(5) |
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DEV_MAC_CFG_MAC_IFG_RX_IFG2(1),
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regs + DEV_MAC_CFG_MAC_IFG);
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/* Set link speed and release all resets */
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writel(DEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(2),
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regs + DEV_DEV_CFG_DEV_RST_CTRL);
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/* Make VLAN aware for CPU traffic */
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writel(ANA_CL_PORT_VLAN_CFG_AWARE_ENA |
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ANA_CL_PORT_VLAN_CFG_POP_CNT(1) |
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MAC_VID,
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priv->regs[ANA_CL] + ANA_CL_PORT_VLAN_CFG(port));
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/* Enable CPU port for any frame transfer */
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setbits_le32(priv->regs[QFWD] + QFWD_SYSTEM_SWITCH_PORT_MODE(port),
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QFWD_SYSTEM_SWITCH_PORT_MODE_PORT_ENA);
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}
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static int ram_init(u32 val, void __iomem *addr)
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{
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writel(val, addr);
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if (wait_for_bit_le32(addr, BIT(1), false, 2000, false)) {
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printf("Timeout in memory reset, reg = 0x%08x\n", val);
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return 1;
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}
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return 0;
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}
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static int servalt_switch_init(struct servalt_private *priv)
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{
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/* Initialize memories */
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ram_init(0x3, priv->regs[QSYS] + QSYS_RAM_CTRL_RAM_INIT);
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ram_init(0x3, priv->regs[ASM] + ASM_RAM_CTRL_RAM_INIT);
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ram_init(0x3, priv->regs[ANA_AC] + ANA_AC_RAM_CTRL_RAM_INIT);
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ram_init(0x3, priv->regs[REW] + REW_RAM_CTRL_RAM_INIT);
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/* Reset counters */
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writel(0x1, priv->regs[ANA_AC] + ANA_AC_STAT_GLOBAL_CFG_PORT_RESET);
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writel(0x1, priv->regs[ASM] + ASM_CFG_STAT_CFG);
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/* Enable switch-core and queue system */
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writel(0x1, priv->regs[QSYS] + QSYS_SYSTEM_RESET_CFG);
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return 0;
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}
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static void servalt_switch_config(struct servalt_private *priv)
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{
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writel(0x55555555, priv->regs[QSYS] + QSYS_CALCFG_CAL_AUTO);
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writel(readl(priv->regs[QSYS] + QSYS_CALCFG_CAL_CTRL) |
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QSYS_CALCFG_CAL_CTRL_CAL_MODE(8),
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priv->regs[QSYS] + QSYS_CALCFG_CAL_CTRL);
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}
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static int servalt_initialize(struct servalt_private *priv)
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{
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int ret, i;
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/* Initialize switch memories, enable core */
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ret = servalt_switch_init(priv);
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if (ret)
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return ret;
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servalt_switch_config(priv);
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for (i = 0; i < MAX_PORT; i++)
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servalt_port_init(priv, i);
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servalt_cpu_capture_setup(priv);
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return 0;
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}
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static inline
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int servalt_vlant_wait_for_completion(struct servalt_private *priv)
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{
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if (wait_for_bit_le32(priv->regs[LRN] + LRN_COMMON_ACCESS_CTRL,
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LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,
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false, 2000, false))
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return -ETIMEDOUT;
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return 0;
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}
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static int servalt_mac_table_add(struct servalt_private *priv,
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const unsigned char mac[ETH_ALEN], int pgid)
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{
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u32 macl = 0, mach = 0;
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/*
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* Set the MAC address to handle and the vlan associated in a format
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* understood by the hardware.
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*/
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mach |= MAC_VID << 16;
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mach |= ((u32)mac[0]) << 8;
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mach |= ((u32)mac[1]) << 0;
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macl |= ((u32)mac[2]) << 24;
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macl |= ((u32)mac[3]) << 16;
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macl |= ((u32)mac[4]) << 8;
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macl |= ((u32)mac[5]) << 0;
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writel(mach, priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG0);
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writel(macl, priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG1);
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writel(LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_ADDR(pgid) |
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LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_TYPE(0x3) |
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LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_COPY |
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LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_CPU_QU(0) |
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LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_VLD |
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LRN_COMMON_MAC_ACCESS_CFG2_MAC_ENTRY_LOCKED,
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priv->regs[LRN] + LRN_COMMON_MAC_ACCESS_CFG2);
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writel(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,
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priv->regs[LRN] + LRN_COMMON_ACCESS_CTRL);
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return servalt_vlant_wait_for_completion(priv);
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}
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static int servalt_write_hwaddr(struct udevice *dev)
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{
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struct servalt_private *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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return servalt_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
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}
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static int servalt_start(struct udevice *dev)
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{
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struct servalt_private *priv = dev_get_priv(dev);
|
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struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const unsigned char mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff,
|
|
0xff };
|
|
int ret;
|
|
|
|
ret = servalt_initialize(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Set MAC address tables entries for CPU redirection */
|
|
ret = servalt_mac_table_add(priv, mac, PGID_BROADCAST);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = servalt_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void servalt_stop(struct udevice *dev)
|
|
{
|
|
}
|
|
|
|
static int servalt_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct servalt_private *priv = dev_get_priv(dev);
|
|
u32 ifh[IFH_LEN];
|
|
u32 *buf = packet;
|
|
|
|
memset(ifh, '\0', IFH_LEN * 4);
|
|
|
|
/* Set DST PORT_MASK */
|
|
ifh[0] = htonl(0);
|
|
ifh[1] = htonl(0x1FFFFF);
|
|
ifh[2] = htonl(~0);
|
|
/* Set DST_MODE to INJECT and UPDATE_FCS */
|
|
ifh[5] = htonl(0x4c0);
|
|
|
|
return mscc_send(priv->regs[QS], servalt_regs_qs,
|
|
ifh, IFH_LEN, buf, length);
|
|
}
|
|
|
|
static int servalt_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct servalt_private *priv = dev_get_priv(dev);
|
|
u32 *rxbuf = (u32 *)net_rx_packets[0];
|
|
int byte_cnt = 0;
|
|
|
|
byte_cnt = mscc_recv(priv->regs[QS], servalt_regs_qs, rxbuf, IFH_LEN,
|
|
false);
|
|
|
|
*packetp = net_rx_packets[0];
|
|
|
|
return byte_cnt;
|
|
}
|
|
|
|
static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
|
|
{
|
|
int i = 0;
|
|
|
|
for (i = 0; i < SERVALT_MIIM_BUS_COUNT; ++i)
|
|
if (miim[i].miim_base == base && miim[i].miim_size == size)
|
|
return miim[i].bus;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void add_port_entry(struct servalt_private *priv, size_t index,
|
|
size_t phy_addr, struct mii_dev *bus)
|
|
{
|
|
priv->ports[index].phy_addr = phy_addr;
|
|
priv->ports[index].bus = bus;
|
|
}
|
|
|
|
static int servalt_probe(struct udevice *dev)
|
|
{
|
|
struct servalt_private *priv = dev_get_priv(dev);
|
|
int i;
|
|
struct resource res;
|
|
fdt32_t faddr;
|
|
phys_addr_t addr_base;
|
|
unsigned long addr_size;
|
|
ofnode eth_node, node, mdio_node;
|
|
size_t phy_addr;
|
|
struct mii_dev *bus;
|
|
struct ofnode_phandle_args phandle;
|
|
|
|
if (!priv)
|
|
return -EINVAL;
|
|
|
|
/* Get registers and map them to the private structure */
|
|
for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
|
|
priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
|
|
if (!priv->regs[i]) {
|
|
debug
|
|
("Error can't get regs base addresses for %s\n",
|
|
regs_names[i]);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
/* Initialize miim buses */
|
|
memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
|
|
SERVALT_MIIM_BUS_COUNT);
|
|
|
|
/* iterate all the ports and find out on which bus they are */
|
|
i = 0;
|
|
eth_node = dev_read_first_subnode(dev);
|
|
for (node = ofnode_first_subnode(eth_node);
|
|
ofnode_valid(node);
|
|
node = ofnode_next_subnode(node)) {
|
|
if (ofnode_read_resource(node, 0, &res))
|
|
return -ENOMEM;
|
|
i = res.start;
|
|
|
|
ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
|
|
&phandle);
|
|
|
|
/* Get phy address on mdio bus */
|
|
if (ofnode_read_resource(phandle.node, 0, &res))
|
|
return -ENOMEM;
|
|
phy_addr = res.start;
|
|
|
|
/* Get mdio node */
|
|
mdio_node = ofnode_get_parent(phandle.node);
|
|
|
|
if (ofnode_read_resource(mdio_node, 0, &res))
|
|
return -ENOMEM;
|
|
faddr = cpu_to_fdt32(res.start);
|
|
|
|
addr_base = ofnode_translate_address(mdio_node, &faddr);
|
|
addr_size = res.end - res.start;
|
|
|
|
/* If the bus is new then create a new bus */
|
|
if (!get_mdiobus(addr_base, addr_size))
|
|
priv->bus[miim_count] =
|
|
servalt_mdiobus_init(addr_base, addr_size);
|
|
|
|
/* Connect mdio bus with the port */
|
|
bus = get_mdiobus(addr_base, addr_size);
|
|
add_port_entry(priv, i, phy_addr, bus);
|
|
}
|
|
|
|
mscc_phy_reset();
|
|
|
|
for (i = 0; i < MAX_PORT; i++) {
|
|
if (!priv->ports[i].bus)
|
|
continue;
|
|
|
|
phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
|
|
PHY_INTERFACE_MODE_NONE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int servalt_remove(struct udevice *dev)
|
|
{
|
|
struct servalt_private *priv = dev_get_priv(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < SERVALT_MIIM_BUS_COUNT; i++) {
|
|
mdio_unregister(priv->bus[i]);
|
|
mdio_free(priv->bus[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops servalt_ops = {
|
|
.start = servalt_start,
|
|
.stop = servalt_stop,
|
|
.send = servalt_send,
|
|
.recv = servalt_recv,
|
|
.write_hwaddr = servalt_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id mscc_servalt_ids[] = {
|
|
{.compatible = "mscc,vsc7437-switch" },
|
|
{ /* Sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(servalt) = {
|
|
.name = "servalt-switch",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mscc_servalt_ids,
|
|
.probe = servalt_probe,
|
|
.remove = servalt_remove,
|
|
.ops = &servalt_ops,
|
|
.priv_auto_alloc_size = sizeof(struct servalt_private),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|