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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
346 lines
8.0 KiB
C
346 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "clk-uniphier.h"
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/**
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* struct uniphier_clk_priv - private data for UniPhier clock driver
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*
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* @base: base address of the clock provider
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* @data: SoC specific data
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*/
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struct uniphier_clk_priv {
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struct udevice *dev;
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void __iomem *base;
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const struct uniphier_clk_data *data;
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};
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static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
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const struct uniphier_clk_gate_data *gate)
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{
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u32 val;
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val = readl(priv->base + gate->reg);
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val |= BIT(gate->bit);
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writel(val, priv->base + gate->reg);
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}
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static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
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const struct uniphier_clk_mux_data *mux,
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u8 id)
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{
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u32 val;
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int i;
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for (i = 0; i < mux->num_parents; i++) {
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if (mux->parent_ids[i] != id)
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continue;
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val = readl(priv->base + mux->reg);
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val &= ~mux->masks[i];
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val |= mux->vals[i];
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writel(val, priv->base + mux->reg);
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return;
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}
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WARN_ON(1);
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}
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static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
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const struct uniphier_clk_mux_data *mux)
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{
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u32 val;
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int i;
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val = readl(priv->base + mux->reg);
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for (i = 0; i < mux->num_parents; i++)
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if ((mux->masks[i] & val) == mux->vals[i])
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return mux->parent_ids[i];
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dev_err(priv->dev, "invalid mux setting\n");
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return UNIPHIER_CLK_ID_INVALID;
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}
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static const struct uniphier_clk_data *uniphier_clk_get_data(
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struct uniphier_clk_priv *priv, u8 id)
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{
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const struct uniphier_clk_data *data;
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for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
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if (data->id == id)
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return data;
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dev_err(priv->dev, "id=%u not found\n", id);
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return NULL;
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}
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static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
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struct uniphier_clk_priv *priv,
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const struct uniphier_clk_data *data)
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{
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const struct uniphier_clk_data *parent_data;
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u8 parent_id = UNIPHIER_CLK_ID_INVALID;
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switch (data->type) {
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case UNIPHIER_CLK_TYPE_GATE:
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parent_id = data->data.gate.parent_id;
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break;
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case UNIPHIER_CLK_TYPE_MUX:
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parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
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break;
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default:
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break;
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}
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if (parent_id == UNIPHIER_CLK_ID_INVALID)
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return NULL;
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parent_data = uniphier_clk_get_data(priv, parent_id);
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WARN_ON(!parent_data);
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return parent_data;
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}
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static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
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const struct uniphier_clk_data *data)
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{
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const struct uniphier_clk_data *parent_data;
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if (data->type == UNIPHIER_CLK_TYPE_GATE)
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uniphier_clk_gate_enable(priv, &data->data.gate);
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parent_data = uniphier_clk_get_parent_data(priv, data);
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if (!parent_data)
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return;
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return __uniphier_clk_enable(priv, parent_data);
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}
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static int uniphier_clk_enable(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_data *data;
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data = uniphier_clk_get_data(priv, clk->id);
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if (!data)
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return -ENODEV;
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__uniphier_clk_enable(priv, data);
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return 0;
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}
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static unsigned long __uniphier_clk_get_rate(
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struct uniphier_clk_priv *priv,
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const struct uniphier_clk_data *data)
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{
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const struct uniphier_clk_data *parent_data;
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if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
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return data->data.rate.fixed_rate;
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parent_data = uniphier_clk_get_parent_data(priv, data);
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if (!parent_data)
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return 0;
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return __uniphier_clk_get_rate(priv, parent_data);
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}
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static unsigned long uniphier_clk_get_rate(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_data *data;
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data = uniphier_clk_get_data(priv, clk->id);
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if (!data)
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return -ENODEV;
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return __uniphier_clk_get_rate(priv, data);
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}
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static unsigned long __uniphier_clk_set_rate(
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struct uniphier_clk_priv *priv,
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const struct uniphier_clk_data *data,
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unsigned long rate, bool set)
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{
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const struct uniphier_clk_data *best_parent_data = NULL;
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const struct uniphier_clk_data *parent_data;
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unsigned long best_rate = 0;
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unsigned long parent_rate;
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u8 parent_id;
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int i;
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if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
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return data->data.rate.fixed_rate;
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if (data->type == UNIPHIER_CLK_TYPE_GATE) {
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parent_data = uniphier_clk_get_parent_data(priv, data);
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if (!parent_data)
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return 0;
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return __uniphier_clk_set_rate(priv, parent_data, rate, set);
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}
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if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
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return -EINVAL;
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for (i = 0; i < data->data.mux.num_parents; i++) {
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parent_id = data->data.mux.parent_ids[i];
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parent_data = uniphier_clk_get_data(priv, parent_id);
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if (WARN_ON(!parent_data))
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return -EINVAL;
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parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
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false);
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if (parent_rate <= rate && best_rate < parent_rate) {
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best_rate = parent_rate;
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best_parent_data = parent_data;
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}
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}
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dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);
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if (!best_parent_data)
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return -EINVAL;
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if (!set)
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return best_rate;
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uniphier_clk_mux_set_parent(priv, &data->data.mux,
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best_parent_data->id);
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return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
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rate, true);
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}
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static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_data *data;
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data = uniphier_clk_get_data(priv, clk->id);
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if (!data)
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return -ENODEV;
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return __uniphier_clk_set_rate(priv, data, rate, true);
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}
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static const struct clk_ops uniphier_clk_ops = {
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.enable = uniphier_clk_enable,
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.get_rate = uniphier_clk_get_rate,
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.set_rate = uniphier_clk_set_rate,
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};
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static int uniphier_clk_probe(struct udevice *dev)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev->parent);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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if (!priv->base)
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return -ENOMEM;
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priv->dev = dev;
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priv->data = (void *)dev_get_driver_data(dev);
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return 0;
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}
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static const struct udevice_id uniphier_clk_match[] = {
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/* System clock */
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{
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.compatible = "socionext,uniphier-ld4-clock",
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.data = (ulong)uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-clock",
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.data = (ulong)uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-clock",
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.data = (ulong)uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-clock",
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.data = (ulong)uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-clock",
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.data = (ulong)uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-clock",
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.data = (ulong)uniphier_ld20_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-clock",
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.data = (ulong)uniphier_ld20_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-clock",
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.data = (ulong)uniphier_pxs3_sys_clk_data,
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},
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/* Media I/O clock */
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{
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.compatible = "socionext,uniphier-ld4-mio-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-sd-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-sd-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-sd-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-sd-clock",
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.data = (ulong)uniphier_mio_clk_data,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_clk) = {
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.name = "uniphier-clk",
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.id = UCLASS_CLK,
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.of_match = uniphier_clk_match,
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.probe = uniphier_clk_probe,
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.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
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.ops = &uniphier_clk_ops,
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};
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