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![Paul Burton](/assets/img/avatar_default.png)
Add initial support for the Ingenic JZ47xx MIPS SoC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
271 lines
6.9 KiB
C
271 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* JZ4780 DDR initialization
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*
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* Copyright (c) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot
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* Copyright (c) 2006-2013 Ingenic Semiconductor
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/jz4780.h>
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#include <mach/jz4780_dram.h>
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static const u32 get_mem_clk(void)
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{
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const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) /
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(JZ4780_MPLL_N * JZ4780_MPLL_OD);
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return mpll_out / JZ4780_SYS_MEM_DIV;
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}
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u32 sdram_size(int cs)
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{
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u32 dw = DDR_DW32 ? 4 : 2;
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u32 banks = DDR_BANK8 ? 8 : 4;
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u32 size = 0;
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if ((cs == 0) && DDR_CS0EN) {
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size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
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if (DDR_CS1EN && (size > 0x20000000))
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size = 0x20000000;
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} else if ((cs == 1) && DDR_CS1EN) {
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size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
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}
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return size;
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}
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static void ddr_cfg_init(void)
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{
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void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
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u32 ddrc_cfg, tmp;
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tmp = DDR_CL;
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if (tmp)
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tmp--;
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if (tmp > 4)
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tmp = 4;
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ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA |
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DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) |
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((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) |
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(DDR_CS0EN << 6) | (DDR_BANK8 << 1) |
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((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) |
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(DDR_CS1EN << 7) | (DDR_BANK8 << 23);
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if (DDR_BL > 4)
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ddrc_cfg |= BIT(21);
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writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG);
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}
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static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config)
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{
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void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
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void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
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unsigned int count = 0, i;
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u32 reg, mask;
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writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR);
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writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0);
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writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1);
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writel(0, ddr_phy_regs + DDRP_ODTCR);
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writel(0, ddr_phy_regs + DDRP_MR2);
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writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0);
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writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1);
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writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2);
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writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0);
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writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1);
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writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2);
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writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) |
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(2 << DDRP_PGCR_CKDV_BIT) |
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(DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT |
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DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX,
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ddr_phy_regs + DDRP_PGCR);
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for (i = 0; i < 8; i++)
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clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9);
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count = 0;
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mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE;
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for (;;) {
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reg = readl(ddr_phy_regs + DDRP_PGSR);
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if ((reg == mask) || (reg == 0x1f))
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break;
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if (count++ == 10000)
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hang();
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}
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/* DQS extension and early set to 1 */
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clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4);
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/* 500 pull up and 500 pull down */
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clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4);
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/* Initialise phy */
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writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST,
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ddr_phy_regs + DDRP_PIR);
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count = 0;
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mask |= DDRP_PGSR_DIDONE;
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for (;;) {
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reg = readl(ddr_phy_regs + DDRP_PGSR);
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if ((reg == mask) || (reg == 0x1f))
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break;
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if (count++ == 20000)
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hang();
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}
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writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR);
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count = 0;
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mask |= DDRP_PGSR_DTDONE;
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for (;;) {
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reg = readl(ddr_phy_regs + DDRP_PGSR);
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if (reg == mask)
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break;
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if (count++ != 50000)
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continue;
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reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR;
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if (reg)
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hang();
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count = 0;
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}
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/* Override impedance */
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clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff,
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((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) |
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((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) |
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DDRP_ZQXCR_ZDEN);
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}
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#define JZBIT(bit) ((bit % 4) * 8)
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#define JZMASK(bit) (0x1f << JZBIT(bit))
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static void remap_swap(int a, int b)
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{
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void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
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u32 remmap[2], tmp[2];
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remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4));
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remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4));
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tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a);
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tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b);
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remmap[0] &= ~JZMASK(a);
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remmap[1] &= ~JZMASK(b);
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writel(remmap[0] | (tmp[1] << JZBIT(a)),
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ddr_ctl_regs + DDRC_REMMAP(a / 4));
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writel(remmap[1] | (tmp[0] << JZBIT(b)),
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ddr_ctl_regs + DDRC_REMMAP(b / 4));
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}
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static void mem_remap(void)
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{
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u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12;
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u32 num = DDR_BANK8 ? 3 : 2;
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if (DDR_CS0EN && DDR_CS1EN)
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num++;
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for (; num > 0; num--)
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remap_swap(0 + num - 1, start + num - 1);
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}
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/* Fetch DRAM config from board file */
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__weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
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{
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return NULL;
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}
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void sdram_init(void)
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{
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const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config();
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void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
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void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
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void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
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u32 mem_clk, tmp, i;
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u32 mem_base0, mem_base1;
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u32 mem_mask0, mem_mask1;
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u32 mem_size0, mem_size1;
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if (!ddr_config)
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hang();
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/* Reset DLL in DDR PHY */
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writel(0x3, cpm_regs + 0xd0);
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mdelay(400);
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writel(0x1, cpm_regs + 0xd0);
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mdelay(400);
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/* Enter reset */
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writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL);
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mem_clk = get_mem_clk();
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tmp = 1000000000 / mem_clk;
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if (1000000000 % mem_clk)
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tmp++;
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tmp = DDR_tREFI / tmp;
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tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1;
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if (tmp > 0xff)
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tmp = 0xff;
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if (tmp < 1)
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tmp = 1;
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writel(0x0, ddr_ctl_regs + DDRC_CTRL);
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writel(0x150000, ddr_phy_regs + DDRP_DTAR);
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ddr_phy_init(ddr_config);
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writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
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writel(0x0, ddr_ctl_regs + DDRC_CTRL);
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ddr_cfg_init();
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for (i = 0; i < 6; i++)
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writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i));
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mem_size0 = sdram_size(0);
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mem_size1 = sdram_size(1);
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if (!mem_size1 && mem_size0 > 0x20000000) {
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mem_base0 = 0x0;
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mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK;
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} else {
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mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff;
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mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
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}
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if (mem_size1) {
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mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
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mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff;
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} else {
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mem_mask1 = 0;
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mem_base1 = 0xff;
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}
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writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0,
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ddr_ctl_regs + DDRC_MMAP0);
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writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1,
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ddr_ctl_regs + DDRC_MMAP1);
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writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
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writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN |
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(tmp << DDRC_REFCNT_CON_BIT),
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ddr_ctl_regs + DDRC_REFCNT);
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writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) |
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(1 << 4) | (1 << 3) | (1 << 2) | (1 << 1),
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ddr_ctl_regs + DDRC_CTRL);
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mem_remap();
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clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40);
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}
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