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https://github.com/brain-hackers/u-boot-brain
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b7f2bbfff6
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
35 lines
706 B
Makefile
35 lines
706 B
Makefile
#
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# Copyright 2014-2015, Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SPL) += spl.o
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ifneq ($(CONFIG_FSL_LSCH3),)
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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else
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ifneq ($(CONFIG_FSL_LSCH2),)
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obj-y += fsl_lsch2_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
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endif
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endif
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ifneq ($(CONFIG_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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ifneq ($(CONFIG_LS1043A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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endif
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ifneq ($(CONFIG_LS1012A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
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endif
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