mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
![Horatiu Vultur](/assets/img/avatar_default.png)
Add device tree based on evaluation board pcb110. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
188 lines
3.7 KiB
Plaintext
188 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,jr2";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,jr2-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,jr2-icpu-intr";
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reg = <0x70 0x94>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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spi0: spi-master@101000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-ssi";
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reg = <0x101000 0x40>;
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num-chipselect = <4>;
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bus-num = <0>;
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reg-io-width = <4>;
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reg-shift = <2>;
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spi-max-frequency = <18000000>; /* input clock */
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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reset@1010008 {
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compatible = "mscc,jr2-chip-reset";
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reg = <0x1010008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,jaguar2-pinctrl";
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reg = <0x1010038 0x90>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 64>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sg0";
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};
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sgpio1_pins: sgpio1-pins {
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pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
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function = "sg1";
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};
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sgpio2_pins: sgpio2-pins {
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pins = "GPIO_30", "GPIO_31",
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"GPIO_32", "GPIO_33";
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function = "sg2";
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};
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uart_pins: uart-pins {
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pins = "GPIO_10", "GPIO_11";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_24", "GPIO_25";
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function = "uart2";
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};
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};
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sgpio: gpio@1010150 {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x1010150 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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gpio-bank-name = "sgpio0_";
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sgpio-clock = <0x14>;
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};
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sgpio1: gpio@101025c {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio1_pins>;
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pinctrl-names = "default";
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reg = <0x101025c 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio1 0 0 64>;
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gpio-bank-name = "sgpio1_";
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sgpio-clock = <0x14>;
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};
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sgpio2: gpio@1010368 {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio2_pins>;
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pinctrl-names = "default";
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reg = <0x1010368 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio2 0 0 64>;
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gpio-bank-name = "sgpio2_";
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sgpio-clock = <0x14>;
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};
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};
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};
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